Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)最新文献_第5页

Application-specific economic analysis of integral passives in printed circuit boards 印刷电路板中集成无源的应用经济分析

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916609

B. Etienne, P. Sandborn

{"title":"Application-specific economic analysis of integral passives in printed circuit boards","authors":"B. Etienne, P. Sandborn","doi":"10.1109/ISAOM.2001.916609","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916609","url":null,"abstract":"This paper summarizes an application-specific economic analysis of the conversion of discrete passive resistors and capacitors to integral passives that are embedded within a printed circuit board. In this study, we assume that integral resistors are printed or plated directly on to wiring layers (as opposed to requiring a dedicated layer), that bypass capacitors are embedded by dielectric substitution into existing reference plane layers, and that singulated nonbypass capacitors are embedded using dedicated layer pair addition. The model presented performs three basic analyses: (1) board size analysis is used to determine board sizes, layer counts, and the number of boards that can be fabricated on a panel; (2) panel fabrication cost modeling including a cost of ownership model is used to determine the impact of throughput changes associated with fabricating integral passive panels; and (3) assembly modeling is used to determine the cost of assembling all discrete components, and their associated inspection and rework. The combination of these three analyses is used to evaluate size/cost trade-offs for an example board.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127245957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

A new approach to the robust wirebonding 一种鲁棒线连接的新方法

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916605

C. Pham, K. Huth

引用次数: 7

Low-CTE materials for printed wiring boards 用于印刷线路板的低cte材料

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916571

T. M. Krziwanek

{"title":"Low-CTE materials for printed wiring boards","authors":"T. M. Krziwanek","doi":"10.1109/ISAOM.2001.916571","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916571","url":null,"abstract":"This paper looks at the approaches of a printed wiring board producer to the challenges of stress-free bare-die assembly and increased reliability. The results of this investigation show that reducing the CTE of PWB base materials is a very effective way to increase the reliability of PWBs. Depending on the application, it may be enough to reduce the CTE in the plane of the board for better interconnection reliability between the PWB and surface-mounted devices. This can be done by using standard materials for the major part of the multilayer and materials with alternative reinforcements for the outer layers. Even better reliability can be attained by building the whole multilayer with materials with low CTE properties in all three dimensions. Current developments in telecommunication, automotive and other markets will raise demand for PWBs with higher component density and reliability. Therefore, low-CTE applications will gain in importance. The development of new materials and further development of new concepts for build-up PWBs is the answer to these challenges. This process has already been started and several products are available, but there is still much work to be done.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123864338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Impact of wafer surface profile on IC packaging 晶圆表面轮廓对IC封装的影响

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916610

J.C.L. Wu, H. Iksan, T. Huang, J.D. Wu, K. Lo

引用次数: 3

High thermally conductive underfill for flip-chip applications 用于倒装芯片应用的高导热底填料

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916547

K. Suzuki, O. Suzuki, K. Muramatu, T. Yuda, K. Isobe, H. Maruyama, H. Fukuyama

引用次数: 1

A study of the insulator material for the interconnection in ALIVH/sup (R)/ substrate ALIVH/sup (R)/衬底互连绝缘子材料的研究

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916568

Y. Kawakita, T. Suzuki, F. Echigo, D. Ando, T. Ishida

{"title":"A study of the insulator material for the interconnection in ALIVH/sup (R)/ substrate","authors":"Y. Kawakita, T. Suzuki, F. Echigo, D. Ando, T. Ishida","doi":"10.1109/ISAOM.2001.916568","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916568","url":null,"abstract":"Current demands in manufacturing of consumer electronics for smaller size, lighter weight and lower cost with high performance are most important. In order to meet these demands, high-density printed circuit boards (PCBs) are strongly required. Under this background, we have developed a new organic PCB called \"ALIVH/sup (R)/\" (any layer interstitial via hole). It realizes electric interconnections by interstitial via holes (IVHs) with cured conductive paste. Due to the ability to form the IVH in any layer and any position, the ALIVH substrate has an ideal IVH structure and is therefore excellent for high-density wiring. In the electric interconnections of ALIVH substrates, we found that it was the most important for the conductive paste to be compressed strongly in the laminating process. We examined one of the compression techniques, using nonwoven aramid paper as a reinforcing material. We studied the properties of nonwoven aramid-epoxy prepreg. As a result of our study, we found that the compression of the prepreg depended on the paper density and the resin content. Moreover, other PCB properties were also influenced by the paper density and the resin content. Therefore, the balance between the interconnection and the other properties is important to ALIVH substrates.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127116723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Study of curing mechanism of epoxy/phenolic system for underfill applications 下填料用环氧/酚醛体系固化机理研究

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916585

Zhuqing Zhang, C. Wong

引用次数: 2

Adhesion study on underfill encapsulant affected by flip chip assembly variables 倒装芯片组装变量对下填料胶粘剂粘附性能影响的研究

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916577

L. Fan, K. Moon, C. Wong

{"title":"Adhesion study on underfill encapsulant affected by flip chip assembly variables","authors":"L. Fan, K. Moon, C. Wong","doi":"10.1109/ISAOM.2001.916577","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916577","url":null,"abstract":"Underfill material is a polymeric adhesive which is used in flip chip devices. It encapsulates the solder joints by filling the gap between silicon die and organic substrate. Within a typical flip chip assembly, there are interfaces between the various components, i.e. substrate, solder mask, flux residue, underfill encapsulant and die passivation layer, etc. Maintaining good adhesion conditions, both as-made and after aging, for these interfaces is vital for the expected performance of the flip chip device assembly, where underfill material is employed to enhance the reliability of the flip-chip device dramatically as compared to a nonunderfilled device. A large portion of a previous adhesion study was focused on the underfill material itself; however, this paper looks into the effects of the different assembly factors, such as solder mask, flux residue, underfill and IC chip passivation, etc., upon the adhesion strength between these interfaces. The influence of some accelerated aging tests on the adhesion durability is also investigated. This could provide device/board level insights into the interfacial adhesion of the flip chip assembly.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125650640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Halogen free packaging materials 无卤素包装材料

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916566

A. Rae, K. Gilleo, C. Moses, S. Ostrow, B. Varnell

引用次数: 4

Let's revise the ASTM method F.459 for wirebonding process control 让我们修改ASTM方法F.459来进行线接过程控制

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916573

C. Pham, K. Huth

引用次数: 1