Application-specific economic analysis of integral passives in printed circuit boards

This paper summarizes an application-specific economic analysis of the conversion of discrete passive resistors and capacitors to integral passives that are embedded within a printed circuit board. In this study, we assume that integral resistors are printed or plated directly on to wiring layers (as opposed to requiring a dedicated layer), that bypass capacitors are embedded by dielectric substitution into existing reference plane layers, and that singulated nonbypass capacitors are embedded using dedicated layer pair addition. The model presented performs three basic analyses: (1) board size analysis is used to determine board sizes, layer counts, and the number of boards that can be fabricated on a panel; (2) panel fabrication cost modeling including a cost of ownership model is used to determine the impact of throughput changes associated with fabricating integral passive panels; and (3) assembly modeling is used to determine the cost of assembling all discrete components, and their associated inspection and rework. The combination of these three analyses is used to evaluate size/cost trade-offs for an example board.