Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)最新文献_第4页

Shear property and microstructure evaluation of Pb-free solder bumps under room temperature and multiple reflow/high temperature aging 室温和多次回流/高温时效下无铅焊点的剪切性能及组织评价

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916600

Li Li, Jin-wook Jang, B. Allmen

{"title":"Shear property and microstructure evaluation of Pb-free solder bumps under room temperature and multiple reflow/high temperature aging","authors":"Li Li, Jin-wook Jang, B. Allmen","doi":"10.1109/ISAOM.2001.916600","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916600","url":null,"abstract":"In this study, bump shear and microstructure evaluations have been performed to characterize Sn-3.5Ag, Sn-3.8Ag-0.7Cu, and Sn-0.7Cu, along with eutectic Sn37Pb. Bump shear strengths were monitored during room temperature aging up to 1000 hrs, and during high temperature storage at 125, 150, and 170/spl deg/C up to 1000 hrs after two and 10 reflows. All bump shear failures were through the solder, indicating that the bump structure interfaces all have good adhesion. Different shear strength was observed with respect to solder alloy composition. At room temperature, the shear strength of eutectic Sn37Pb decreased by 25% after 51 days aging after reflow while the shear strength of all the Pb-free alloys decreased slightly by 5-8%. Microstructure evolution with aging time was observed and correlated to shear strength change at room temperature. The shear strength of both Sn-3.5Ag and Sn-3.8Ag-0.7Cu solders became lower after two reflows but were not affected up to 10 reflows. The shear strength of Sn-37Pb and Sn-0.7Cu solder had no change after either multiple reflows or high temperature storage. Solder bump microstructure under these conditions was characterized. Chemical reactions between solders and under-bump metallurgy (UBM) interactions during multiple reflows and high temperature storage were also investigated. Sn-37Pb solder consumed less Cu UBM than all other Pb-free solders during reflow. However, it consumed more Cu after solid state annealing. An optimal Pb-free alloy (Sn-0.7Cu) is proposed based on this study and previously reported mechanical property and thermal fatigue reliability evaluations for flip chip solder joints.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128507299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Interconnection technique of ALIVH/sup (R)/ substrate ALIVH/sup (R)/基板互连技术

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916543

T. Suzuki, S. Tomekawa, T. Ogawa, D. Andoh, M. Tanahashi, T. Ishida

引用次数: 13

Thermosetting and thermoplastic bisphenol A epoxy/phenoxy resin as encapsulant material 热固性和热塑性双酚A环氧/苯氧基树脂作为包封材料

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916580

L. Fan, C. Wong

{"title":"Thermosetting and thermoplastic bisphenol A epoxy/phenoxy resin as encapsulant material","authors":"L. Fan, C. Wong","doi":"10.1109/ISAOM.2001.916580","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916580","url":null,"abstract":"Polymer materials have found extensive applications as encapsulants in the microelectronics packaging industry, especially the epoxy resin systems for die attach adhesive, glob top, underfill, etc. However, normally only thermosetting systems have been widely employed, which could transform into infusible 3D networks during the curing process. In this paper, we explore the possibility of using thermoplastic materials and their combination with thermosetting materials as encapsulants for some specific end microelectronic products, as they would demonstrate some process/property advantages over the fully thermosetting counterparts, a potentially tremendous economic/cost concern. Both thermosetting and thermoplastic epoxy resins were studied for their adhesion as well as adhesion durability capability. The chemistry is based on poly(bisphenol A-co-epichlorohydrin), including the basic liquid resin and the advanced solid resin of different molecular weight, and the so-called phenoxy resin of very high molecular weight. In order to target a practically feasible formulation that would operate with an actual industrial line, the development work was implemented by combining the thermosetting basic liquid epoxy resin with the thermoplastic free radical polymerizable system, which appeared to be a quite promising approach for both product processibility and application performance.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115210947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

PWB surface finish process development to enhance the reliability of the solder joint strength 铜压板表面光洁度工艺的发展，提高了焊点强度的可靠性

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916569

Y. Watanabe

{"title":"PWB surface finish process development to enhance the reliability of the solder joint strength","authors":"Y. Watanabe","doi":"10.1109/ISAOM.2001.916569","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916569","url":null,"abstract":"PWBs for mobile phones have widely applied electroless nickel/immersion gold plating (EL Ni/Au) for keypads. However, the solder joint strength tends to be weak when EL Ni/Au plating is applied to the PWB pads, especially BGA/CSP pads. The fracture mode of intermetallic layers between solder and nickel is observed on weakened pads. We have been analyzing the factors of this problem, and were able to resolve it to some extent. The solder joint strength depends on the phosphorus content of the nickel film. We found that the fracture mode of the intermetallic layers appears when the phosphorus content of the nickel film is too high. We also found that the immersion gold bath condition is another factor. We have been using this information to improve our EL Ni/Au line. We have also developed a new surface finish utilizing copper, which is known to enhance the reliability of the solder ball-joint strength. The newly established surface finish consists of selectively coating OSP over those copper pads where reliability of the solder ball joint strength is needed. The EL Ni/Au is plated on keypads. We call this process \"selective OSP\". This paper introduces the reliability data for solder joint strength, the design rules, and production results of selective OSP.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134224089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Improvements in adhesion using new Cu treatment method for substrates [packaging] 采用新型Cu处理方法改善基板的附着力[封装]

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916570

J. Miller, T. Thompson

{"title":"Improvements in adhesion using new Cu treatment method for substrates [packaging]","authors":"J. Miller, T. Thompson","doi":"10.1109/ISAOM.2001.916570","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916570","url":null,"abstract":"This report discusses the differences between the current jet scrub (mechanical) and newly used chemical etch processes in the substrate manufacturing process to etch copper. This newly proposed process is expected to increase package moisture performance by creating a rougher surface finish, resulting in interlocking of the solder mask to the copper. The differences between the two processes are covered in detail. The report discusses moisture results obtained, comparing the two processes with existing package materials in a BGA. The mold compound, nonconductive die attach and jet scrub substrate have achieved moisture sensitivity level 1 at 220/spl deg/C reflow in some cases of optimized substrate design. The process performance is benchmarked using four substrate suppliers used in the industry. Package moisture performance improvements are critical to passing higher reflow temperature requirements such as 240/spl deg/C and 260/spl deg/C for Pb-free solutions for environmentally sensitive products in the wireless and palm pilot communications market. Also included is a discussion of how the chemical etch performs based on other assembly quality measures such as wire ball shear, wire pull, solder ball adhesion and solder joint reliability. This new process is not expected to affect cost or cycle time and is seen as an improvement in overall product quality and reliability. However, due to varying experience with BGA moisture performance, especially in cases of large die to package ratios, it is hopeful that the process will provide more consistent results on the package.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115167937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process 采用低成本、高通量倒装芯片组装工艺的衬底设计对下填空的影响

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916548

D. Milner, D. Baldwin

{"title":"Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process","authors":"D. Milner, D. Baldwin","doi":"10.1109/ISAOM.2001.916548","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916548","url":null,"abstract":"Voiding is a concern in low cost, high throughput, or \"no-flow\" flip chip assembly. This process involves chip placement directly on the pad site with pre-dispensed no-flow underfill on it. The forced motion causes a convex flow front to pass over pad and mask-opening features, promoting void capture. This paper determines the effects of substrate design on underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing, including pad height, solder mask opening height, pad/solder mask opening separation, pad pitch, chip placement speed, and underfill viscosity. Test substrates were designed and manufactured at Georgia Tech's Packaging Research Center to ensure process control. The design consisted of 6 factors with a mix of levels for each. These included four levels of copper pad heights, two solder mask opening heights, three pad/solder mask separation distances between copper pad and solder mask opening edges, three feature (pad/mask openings) pitches, two chip placement speeds and four pad/mask geometries separated into pad site quadrants. The experiments involve placement of a transparent glass chip on the pad site through a predispensed no-flow underfill. Subsequent flow of the underfill is carefully recorded and resultant voids are logged and analyzed. The response variable is defined as the number of voids created in the process, and is further analyzed for the location and any visible modes of void formation. Thus, improved substrate designs can be derived.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116576409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Reliability and Au embrittlement of lead free solders for BGA applications BGA应用中无铅焊料的可靠性和金脆度

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916565

A. Syed

{"title":"Reliability and Au embrittlement of lead free solders for BGA applications","authors":"A. Syed","doi":"10.1109/ISAOM.2001.916565","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916565","url":null,"abstract":"Pb-free solder for electronics assemblies is fast becoming a reality, primarily because of market driven forces. This affects the entire electronic manufacturing industry, from component supplier to equipment manufacturer. While the industry has identified possible alternates to Sn-Pb solder alloy, much work still needs to be done, especially in the area of component and board level reliability, solder/surface interactions, and assembly process development. The reliability of Pb-free solder joints for BGA applications under temperature cycle conditions for three different packages is compared in this paper. Two Sn-Ag-Cu compositions are considered and their reliability is compared with Sn-Pb alloy. In addition, ball shear testing was performed after 0, 24, 48, 96, 192, 384, and 504 hours of high temperature aging. The results indicate that the solder joint reliability generally improves when Pb-free solder is used; however, the degree of improvement is package dependent. The ball shear data also favors Sn-Ag-Cu alloy over Sn-Pb alloy. The data also indicates that using Sn-Ag-Cu alloy for solder balls can possibly eliminate the Au embrittlement issue, often encountered in BGA type packages with Sn-Pb balls.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126085183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

Colloidal processing of polymer ceramic nanocomposites for integral capacitors 集成电容器用聚合物陶瓷纳米复合材料的胶体加工

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916608

H. Windlass, P. Raj, D. Balaraman, Swapan K. Bhattacharya, Rao Tummala

{"title":"Colloidal processing of polymer ceramic nanocomposites for integral capacitors","authors":"H. Windlass, P. Raj, D. Balaraman, Swapan K. Bhattacharya, Rao Tummala","doi":"10.1109/ISAOM.2001.916608","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916608","url":null,"abstract":"Polymer ceramic composites form a suitable material system for low temperature fabrication of embedded capacitors appropriate for MCM-L technology. Improved electrical properties such as permittivity can be achieved by efficient filling of polymers with high dielectric constant ceramic powders such as lead magnesium niobate-lead titanate (PMNPT) and barium titanate (BT). Photodefinable epoxies as the matrix polymer allow fine feature definition of the capacitor elements by conventional lithography techniques. The optimum weight percent of dispersant is tuned by monitoring the viscosity of the suspension. The dispersion mechanism (steric and electrostatic contributions) in a slightly polar solvent such as PGMEA is investigated from electrophoretic measurements. A high positive zeta potential is observed in the suspension, which suggests a strong contribution of electrostatic stabilization. By optimizing the particle packing using a bimodal distribution and modified processing methodology, dielectric constant greater than 135 was achieved (PMN-PT-epoxy). Suspensions are made with the lowest PGMEA content to ensure the efficiency of the dispersion and efficient particle packing in the dried film. Improved colloidal processing of nanoparticle-filled epoxy is a promising method to obtain ultra-thin capacitor films (<2 /spl mu/m) with high capacitance density and improved yield. Capacitance of 35 nF/cm/sup 2/ was achieved with the thinnest films (2.5-3.0 /spl mu/m).","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129810068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 90

No-flow underfill formulation using different epoxy resin combination 采用不同环氧树脂组合的无流底填料配方

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916579

L. Fan, W. Reed, C. Wong

{"title":"No-flow underfill formulation using different epoxy resin combination","authors":"L. Fan, W. Reed, C. Wong","doi":"10.1109/ISAOM.2001.916579","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916579","url":null,"abstract":"The no-flow underfill mechanism has been devised as a potential replacement for the conventional capillary flow process, where the underfill material is applied to the substrate before the chip-substrate interconnection is established. During the reflow step, the solder joints are formed prior to full curing of the underfill material. Extensive exploration has been devoted to the potential chemical systems for the no-flow underfill application in our group, and typically those no-flow underfill materials are liquid epoxy resins formulated with an appropriate curing system to fit with the solder reflow profile. Other types of epoxy resin, either liquid or solid at room temperature, have been combined with the basic liquid epoxy resin, to study the viscosity, curing profile, glass transition temperature, modulus and coefficient of thermal expansion. The liquid-liquid thermal shock tests for these formulations have also been conducted for evaluation of the preferred formulation components and loading amount. This will help to provide more material options for no-flow underfill encapsulant development.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129005527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

RF electrical simulation of embedded capacitor 嵌入式电容器的射频电学仿真

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562) Pub Date : 2001-03-11 DOI: 10.1109/ISAOM.2001.916590

Y. Rao, J. Qu, C. Wong

{"title":"RF electrical simulation of embedded capacitor","authors":"Y. Rao, J. Qu, C. Wong","doi":"10.1109/ISAOM.2001.916590","DOIUrl":"https://doi.org/10.1109/ISAOM.2001.916590","url":null,"abstract":"Embedded passives have many advantages, such as: improving packaging efficiency and electrical performance, reducing the use of PWB real estate, eliminating assembly to board, minimizing solder joint failure and enhanced reliability. The trend of miniaturisation of electronic products requires use of embedded passive technology. The design of embedded passives is very important to its practical application. However, there is still no mature commercial computer aided design (CAD) tool available for embedded passive design. The objective of this research is to conduct computer simulation and modeling for embedded capacitors and resistors. The commercial finite element software ANSYS and electric simulation software SPICE were used for the modeling work, which includes electric and thermo-mechanical analyses, the frequency response simulation, and the electric interference prediction of embedded capacitor and resistors. Attention was paid to the effects of material properties and the geometry of the embedded passives. The finite-element method (FEM) model and SPICE simulation provide a good picture of the distribution, electric performance and tolerance of embedded passives. As such, FEM and SPICE are very helpful for the design and manufacture process.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"463 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122790906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7