{"title":"采用低成本、高通量倒装芯片组装工艺的衬底设计对下填空的影响","authors":"D. Milner, D. Baldwin","doi":"10.1109/ISAOM.2001.916548","DOIUrl":null,"url":null,"abstract":"Voiding is a concern in low cost, high throughput, or \"no-flow\" flip chip assembly. This process involves chip placement directly on the pad site with pre-dispensed no-flow underfill on it. The forced motion causes a convex flow front to pass over pad and mask-opening features, promoting void capture. This paper determines the effects of substrate design on underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing, including pad height, solder mask opening height, pad/solder mask opening separation, pad pitch, chip placement speed, and underfill viscosity. Test substrates were designed and manufactured at Georgia Tech's Packaging Research Center to ensure process control. The design consisted of 6 factors with a mix of levels for each. These included four levels of copper pad heights, two solder mask opening heights, three pad/solder mask separation distances between copper pad and solder mask opening edges, three feature (pad/mask openings) pitches, two chip placement speeds and four pad/mask geometries separated into pad site quadrants. The experiments involve placement of a transparent glass chip on the pad site through a predispensed no-flow underfill. Subsequent flow of the underfill is carefully recorded and resultant voids are logged and analyzed. The response variable is defined as the number of voids created in the process, and is further analyzed for the location and any visible modes of void formation. Thus, improved substrate designs can be derived.","PeriodicalId":321904,"journal":{"name":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process\",\"authors\":\"D. Milner, D. Baldwin\",\"doi\":\"10.1109/ISAOM.2001.916548\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Voiding is a concern in low cost, high throughput, or \\\"no-flow\\\" flip chip assembly. This process involves chip placement directly on the pad site with pre-dispensed no-flow underfill on it. The forced motion causes a convex flow front to pass over pad and mask-opening features, promoting void capture. This paper determines the effects of substrate design on underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing, including pad height, solder mask opening height, pad/solder mask opening separation, pad pitch, chip placement speed, and underfill viscosity. Test substrates were designed and manufactured at Georgia Tech's Packaging Research Center to ensure process control. The design consisted of 6 factors with a mix of levels for each. These included four levels of copper pad heights, two solder mask opening heights, three pad/solder mask separation distances between copper pad and solder mask opening edges, three feature (pad/mask openings) pitches, two chip placement speeds and four pad/mask geometries separated into pad site quadrants. The experiments involve placement of a transparent glass chip on the pad site through a predispensed no-flow underfill. Subsequent flow of the underfill is carefully recorded and resultant voids are logged and analyzed. The response variable is defined as the number of voids created in the process, and is further analyzed for the location and any visible modes of void formation. Thus, improved substrate designs can be derived.\",\"PeriodicalId\":321904,\"journal\":{\"name\":\"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-03-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISAOM.2001.916548\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISAOM.2001.916548","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process
Voiding is a concern in low cost, high throughput, or "no-flow" flip chip assembly. This process involves chip placement directly on the pad site with pre-dispensed no-flow underfill on it. The forced motion causes a convex flow front to pass over pad and mask-opening features, promoting void capture. This paper determines the effects of substrate design on underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing, including pad height, solder mask opening height, pad/solder mask opening separation, pad pitch, chip placement speed, and underfill viscosity. Test substrates were designed and manufactured at Georgia Tech's Packaging Research Center to ensure process control. The design consisted of 6 factors with a mix of levels for each. These included four levels of copper pad heights, two solder mask opening heights, three pad/solder mask separation distances between copper pad and solder mask opening edges, three feature (pad/mask openings) pitches, two chip placement speeds and four pad/mask geometries separated into pad site quadrants. The experiments involve placement of a transparent glass chip on the pad site through a predispensed no-flow underfill. Subsequent flow of the underfill is carefully recorded and resultant voids are logged and analyzed. The response variable is defined as the number of voids created in the process, and is further analyzed for the location and any visible modes of void formation. Thus, improved substrate designs can be derived.