{"title":"Negative drain pulse stress induced two-stage degradation of P-channel poly-Si thin-film transistors","authors":"Xiaowei Lu, Mingxiang Wang, Meng Zhang, M. Wong","doi":"10.1109/IPFA.2011.5992756","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992756","url":null,"abstract":"Negative drain pulse stress induced degradation in p-channel poly-Si thin-film transistors (TFTs) was systematically investigated. On-state current (ION) exhibits two-stage degradation behaviors. In the first-stage degradation, electron injection related equivalent DC effect is responsible for the degradation behavior. While in the second-stage, based on a previously proposed PN junction degradation model, degradation behavior can be well understood, which is controlled by dynamic hot carrier (HC) degradation mechanism.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115075705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wu Chunlei, M. Motohiko, Winter Wang, G. Song, Wu Miao, T. Li, Yung-II Joe
{"title":"Resistive vias defect localization methodology in failure analysis","authors":"Wu Chunlei, M. Motohiko, Winter Wang, G. Song, Wu Miao, T. Li, Yung-II Joe","doi":"10.1109/IPFA.2011.5992711","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992711","url":null,"abstract":"Generally, it is very difficult to locating a resistive via defect in function failure analysis in CMOS circuit. This type defect could not be located directly by Photon emission microscopy analysis or other failure analysis techniques. In this paper, a useful method is introduced to show how to locate a resistive via defect. Some cases are presented in detail. And some valuable experiences are shared which could help us locate a resistive via defect quickly.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"113 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120825777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. S. Wei, C. Teo, H. B. Chong, S.H. Lim, V. Narang, J. Chin, M. Ong
{"title":"Back-side De-processing using CMP for bulk silicon 40-nm graphics processors","authors":"M. S. Wei, C. Teo, H. B. Chong, S.H. Lim, V. Narang, J. Chin, M. Ong","doi":"10.1109/IPFA.2011.5992750","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992750","url":null,"abstract":"A back-side de-processing process by chemical mechanical polishing (CMP) is developed. The process has been optimized to produce repeatable results. The process is capable of exposing the circuitry of the die uniformly and is able to target more than one area for units with multiple defect locations; front-side de-processing process has difficulty achieving the same results due to the unevenness of the die","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"8 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126126357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of low-frequency noise in a-Si:H thin-film transistor by using a unified model","authors":"Y. Son, Jaehong Lee, Jaeho Lee, Hyungcheol Shin","doi":"10.1109/IPFA.2011.5992738","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992738","url":null,"abstract":"Low-frequency noise characteristics are investigated in top contact type a-Si:H TFT. For analysis of low-frequency noise data, the unified noise model is applied which combine the carrier number and mobility fluctuations. These two mechanisms are confirmed as a main element of noise in a-Si:H TFT by using current-voltage (I–V) measurement and noise analysis. From the measured low-frequency noise characteristics, the effective trap density and scattering coefficient are extracted by using the unified noise model.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130106126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Chiu, Jun-Jea Feng, W. Shih, Po-Yueh Cheng, Chih-Yao Huang
{"title":"Conduction mechanisms and reliability characteristics in MgO resistive switching memory devices","authors":"F. Chiu, Jun-Jea Feng, W. Shih, Po-Yueh Cheng, Chih-Yao Huang","doi":"10.1109/IPFA.2011.5992775","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992775","url":null,"abstract":"In this work, the resistive switching memory devices based on MgO thin film were fabricated and investigated. A forming electric field of about 2.36 MV/cm is required to induce bipolar resistive switching characteristic of the Pt/MgO/Pt metal-insulator-metal (MIM) diodes. At room temperature, the set and reset electric fields are about 1.5 MV/cm and −0.9 MV/cm, respectively. After the electroforming process, the resistance ratio of high resistance state (HRS) and low resistance state (LRS) is on the order of 105. The temperature dependence of current density-electric field (J-E) characteristics indicates that the dominant conduction mechanism is the hopping conduction and the Ohmic conduction in HRS and LRS, respectively. Accordingly, the hopping distance, trap energy level, and electron mobility in MgO films are obtained. In addition, the reliability characteristics of program/erase cycling endurance, data retention, and read durability of the MgO-based MIM memory devices were measured.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130159365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Metal pad failure phenomena of biosensor due to spontaneous nickel silicide formation","authors":"B. Lee, J. Oh, S. Lee","doi":"10.1109/IPFA.2011.5992763","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992763","url":null,"abstract":"A FET (Field Effect Transistor) biosensor chip for an early diagnosis of disease was fabricated using semiconductor process. Metal pad failure phenomena were found after pad metal deposition process. The electrical I-V performance and cross-sectional TEM inspection were done to find out the root cause of this failure. The nickel silicide growth between Ni UBM (Under Bump Metal) and Si substrate was found. The root cause of this metal pad failure was proved to be the interfacial spontaneous nickel silicide reaction between Ni pad and top Si layers.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130941278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Phase transformation of programmed NiSi electrical fuse: Diffusion, agglomeration and thermal stability","authors":"Jongwoo Park, Hanbyul Kang, G. Kim, Min Kim","doi":"10.1109/IPFA.2011.5992800","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992800","url":null,"abstract":"An advanced CMOS technology process reliability qualification especially for the NiSi poly gated electrical fuse (eFuse) consists of electrical characterization, physical analyses and reliability evaluations. In this paper, insights are given on microstructural behaviors of the programmed NiSi poly gated eFuse induced by the high temperature storage (HTS) test. Both ex- and in-situ transmission electron microscopy (TEM) reveal that the improved post-resistance of the programmed eFuse is attributed to the low temperature growth of Ni3Si2 during HTS test at 250°C. In addition, the Ni agglomeration, the propensity of Ni3Si2 formation on the programmed eFuse with and without void appearance on the fuse link, is comprehensively investigated in conjunction with the eFuse reliability.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127945867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application of X-Ray MicroCT for non-destructive failure analysis and package construction characterization","authors":"Morgan Cason, R. Estrada","doi":"10.1109/IPFA.2011.5992732","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992732","url":null,"abstract":"Several of the critical drawbacks to existing failure analysis imaging techniques, including the low resolution of common non-destructive techniques and the destructiveness and slow speed of FIB/SEM, can be resolved by using X-Ray Micro Computed Tomography (MicroCT) as a complementary technique. In this the paper, we describe examples of the use of X-Ray MicroCT following TDR as non-destructive technique to isolate solderability and bump void failure mechanisms. Also, use of X-Ray MicroCT for package construction analysis is described.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114113850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Failure of gold and copper ball bonds due to intermetallic oxidation and corrosion","authors":"C. Breach, Ng Hun Shen, T. Lee, R. Holliday","doi":"10.1109/IPFA.2011.5992790","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992790","url":null,"abstract":"Strong interest in the replacement of gold bonding wire by copper in microelectronics packaging has highlighted poor performance of copper wire under moist conditions. Attempts have been made to address this problem by coating copper wire with palladium, which may be a solution for some applications but ignores the fundamental reasons for the poor performance of copper wire. Gold and copper ball bonds were isothermally aged under moist conditions (85°C and 85% relative humidity (RH)) in an effort to better understand the corrosion mechanisms. This paper presents ideas on the origins of the moisture sensitivity of copper and gold ball bonds on aluminium alloy bond pads, drawing on experimental data from this study, results from recently published literature and established knowledge on moisture induced degradation of intermetallics.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131384221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Law Che Seong, Y. Seng, Kaneasan Edumban, Lee Meng Chuan, S.F.C. Kean
{"title":"Review on induced CDM-ESD test methodologies for flash memory device","authors":"Law Che Seong, Y. Seng, Kaneasan Edumban, Lee Meng Chuan, S.F.C. Kean","doi":"10.1109/IPFA.2011.5992714","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992714","url":null,"abstract":"During CDM-ESD test, misalignment may occur between the discharge pin and the DUT terminal, especially when the package size shrinks down. We investigated the effect of top ball touch (non-misaligned) and side ball touch (misaligned) on the electrical characteristics of memory devices. The experimental data were analyzed using statistical hypothesis tests and supported by the physics theory of Gauss' Law. We also studied the impact of Mylar dielectric film on the device performance.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127618561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}