2009 International Symposium on VLSI Technology, Systems, and Applications最新文献

Reliability of planar and FinFET SONOS devices for NAND flash applications - Field enhancement vs. barrier engineering 用于NAND闪存应用的平面和FinFET SONOS器件的可靠性-场增强与屏障工程

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159336

T. Hsu, H. Lue, S. Lai, Y. King, K. Hsieh, Rich Liu, Chih-Yuan Lu

{"title":"Reliability of planar and FinFET SONOS devices for NAND flash applications - Field enhancement vs. barrier engineering","authors":"T. Hsu, H. Lue, S. Lai, Y. King, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/VTSA.2009.5159336","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159336","url":null,"abstract":"The reliability of sub-40nm SONOS NAND devices with various tunnel oxide thickness and FinFET structures are studied for future NAND Flash application. SONOS intrinsically has slow erase speed and high erase saturation for tunnel oxide ranging from 25 to 45 Å. Furthermore, the endurance degradation occurs very early at low P/E≪10, owing to the nature of electron de-trapping mechanism at tunnel oxide ≫ 20A. Thus planar SONOS is not suitable for NAND Flash applications. On the other hand, when SONOS is applied to FinFET structure, significantly faster erase speed is obtained, owing to the field enhancement effect. However, it is still hard to erase below the initial Vt. We conclude that barrier engineering, such as BE-SONOS is more efficient in providing faster erase speed at lower erase voltages without endurance degradation. We also estimated the large density (4Mb) array distribution of sub-40 nm SONOS and BE-SONOS devices, and found that the distribution width is quite insensitive to the tunnel oxide thickness. This suggests that for future scaled NAND devices the edge effect is more important in determining the P/E distribution than the tunnel oxide thickness variation.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123045952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

An investigation about the limitation of strained-Si technology 应变硅技术的局限性研究

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159277

M. Liao, L. Yeh, J. C. Lu, M. H. Yu, L. T. Wang, J. Wu, P. Jeng, T. Lee, S. Jang

引用次数: 1

Low capacitance approaches for 22nm generation Cu interconnect 22nm代铜互连的低电容方法

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159288

T. Bao, H. Chen, C.J. Lee, H. Lu, S. Shue, C. Yu

引用次数: 5

High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond 高κ/金属栅极低功耗批量技术-标准CMOS逻辑电路，微处理器关键路径副本和45纳米及以上SRAM的性能评估

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159305

D. Park, K. Stein, K. Schruefer, Y. Lee, J. Han, W. Li, H. Yin, C. Pacha, N. Kim, M. Ostermayr, M. Eller, S. Kim, K. Kim, S. Han, K. von Arnim, N. Moumen, M. Hatzistergos, T. Tang, R. Loesing, X. Chen, D. Jaeger, H. Zhuang, J. Chen, W. Yan, T. Kanarsky, M. Chowdhury, J. Haetty, D. Schepis, M. Chudzik, V.-Y. Theon, S. Samavedam, V. Narayanan, M. Sherony, R. Lindsay, A. Steegen, R. Divakaruni, M. Khare

{"title":"High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond","authors":"D. Park, K. Stein, K. Schruefer, Y. Lee, J. Han, W. Li, H. Yin, C. Pacha, N. Kim, M. Ostermayr, M. Eller, S. Kim, K. Kim, S. Han, K. von Arnim, N. Moumen, M. Hatzistergos, T. Tang, R. Loesing, X. Chen, D. Jaeger, H. Zhuang, J. Chen, W. Yan, T. Kanarsky, M. Chowdhury, J. Haetty, D. Schepis, M. Chudzik, V.-Y. Theon, S. Samavedam, V. Narayanan, M. Sherony, R. Lindsay, A. Steegen, R. Divakaruni, M. Khare","doi":"10.1109/VTSA.2009.5159305","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159305","url":null,"abstract":"This paper presents performance evaluation of high-κ/metal gate (HK/MG) process on an industry standard 45nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in PFET drive current when compared with industry standard 45nm Poly/SiON devices. No additional stress elements were used for this performance gain. The critical path circuits of this low power microprocessor built with HK/MG show dynamic performance gain over 50% at same supply voltage and 36% lower dynamic energy at same performance. Superior SRAM minimum operating voltage characteristics are achieved due to Vt variability reduction from HK/MG. Analog circuit functionality is demonstrated by a fully integrated PLL circuitry without any modification to process.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116498450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Boron carbon nitride film containing hydrogen for 2nm node low-k interconnection 含氢硼碳氮化膜用于2nm节点低k互连

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159270

H. Aoki, T. Masuzumi, M. Hara, D. Watanabe, C. Kimura, T. Sugino

引用次数: 2

High performance metal/insulator/metal capacitors using HfTiO as dielectric 高性能金属/绝缘体/金属电容器采用HfTiO作为电介质

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159294

H. Hsu, Chun‐Hu Cheng, B. Tsui

引用次数: 4

Extending spectroscopic ellipsometry for identification of electrically active defects in Si/SiO2/high-k/metal gate stacks 扩展椭圆偏振光谱法识别Si/SiO2/高k/金属栅堆中的电活性缺陷

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159291

J. Price, G. Bersuker, P. Lysaght, H. Tseng

引用次数: 4

Characterization of poly-Silicon emitter BJTs as access devices for Phase Change Memory 多晶硅发射极bjt作为相变存储器接入器件的特性研究

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159278

B. Rajendran, M. Breitwisch, R. Cheek, M. Lee, Y. Shih, H. Lung, C. Lam

引用次数: 6

Dopant and thermal interaction on SPE formed SiC for NMOS performance enhancement 掺杂剂和热相互作用对固相萃取形成的碳化硅性能的增强

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159275

P. W. Liu, T. Kuo, C. I. Li, Y. R. Wang, R. Huang, C. Tsai, C. T. Tsai, G. H. Ma

引用次数: 0

Multiple electron beam maskless lithography for high-volume manufacturing 用于大批量生产的多电子束无掩模光刻技术

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159308

Jack J. H. Chen, S.J. Lin, T. Fang, S. Chang, F. Krečinić, B. Lin

引用次数: 3