2009 International Symposium on VLSI Technology, Systems, and Applications最新文献

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Successful integration scheme of cost effective dual embedded stressor featuring carbon implant and solid phase epitaxy for high performance CMOS 基于碳植入和固相外延的高性价比双嵌入式应力源集成方案
2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159276
M. Nishikawa, K. Okabe, K. Ikeda, N. Tamura, H. Maekawa, M. Umeyama, H. Kurata, M. Kase, K. Hashimoto
{"title":"Successful integration scheme of cost effective dual embedded stressor featuring carbon implant and solid phase epitaxy for high performance CMOS","authors":"M. Nishikawa, K. Okabe, K. Ikeda, N. Tamura, H. Maekawa, M. Umeyama, H. Kurata, M. Kase, K. Hashimoto","doi":"10.1109/VTSA.2009.5159276","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159276","url":null,"abstract":"We have developed a device integration scheme for embedded silicon carbon (Si:C) SD structures induced by the solid phase epitaxy (SPE) technique. Our integration scheme comprises a combination of three key processes: carbon ion implantation (I/I) with Ge pre-amorphization implantation (PAI), sRTA and LSA. The guideline of our scheme is as follows. First, carbon I/I with Ge PAI plays large roll in this scheme since we can independently control both damage and stressor. Second, Ge PAI prior to carbon I/I is also performed to realize a steep carbon profile. Third, the embedded Si:C is required to be positioned beneath the Rp of n+dopant to maximally utilize the low resistance deep SD I/I region. Finally, optimizing thermal budget enables us to suppress both carbon clustering and residual defects induced by Ge PAI without a degradation of Vth-rolloff characteristics and a strain relaxation in embedded SiGe (eSiGe) in PMOSFETs. By using this scheme, we have controlled both parasitic resistance and junction leakage current simultaneously. In addition, UV-Raman spectroscopy and HR-XRD clarified the achievement of more than 1 at% effective substitutional carbon concentration by this scheme. Consequently, a 5.1% improvement in Ion of NMOSFETs for Ioff = 100 nA/µm at Vd = 1.0 V and Ion = 1154 µA/µm was obtained. For PMOSFETs, thanks to an optimized annealing process, strain relaxation in eSiGe was avoided, and thus Ion = 818 µA/µm for Ioff = 100 nA/µm at Vdd = 1.0 V, was obtained. We have successfully demonstrated the CMOS integration with a cost-effective “dual” embedded stressor.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131735705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ge shallow junction formation by As implantation and flash lamp annealing 砷注入和闪光灯退火形成锗浅结
2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159271
K. Osada, T. Fukunaga, K. Shibahara
{"title":"Ge shallow junction formation by As implantation and flash lamp annealing","authors":"K. Osada, T. Fukunaga, K. Shibahara","doi":"10.1109/VTSA.2009.5159271","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159271","url":null,"abstract":"Shallow, about 20 nm, depth n+/p junction of Ge was successfully fabricated by As+ implantation and FLA. Since the junction depth was limited by implantation energy, much shallower junction would be fabricated by reducing the energy. High potential of arsenic as a dopant was clearly demonstrated, although FLA parameters were not optimized yet. Since SPE retardation was found in the specimens with PAI, other channeling suppression technique should be found.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133051501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A physics-based compact model of quantum-mechanical effects for thin cylindrical Si-Nanowire MOSFETs 薄圆柱形硅纳米线mosfet量子力学效应的基于物理的紧凑模型
2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159313
B. Cousin, O. Rozeau, M. Jaud, J. Jomaah
{"title":"A physics-based compact model of quantum-mechanical effects for thin cylindrical Si-Nanowire MOSFETs","authors":"B. Cousin, O. Rozeau, M. Jaud, J. Jomaah","doi":"10.1109/VTSA.2009.5159313","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159313","url":null,"abstract":"Since we know that quantum-mechanical effects are predominant in surrounding-gate MOSFETs, a model should be developed. For the first time, this paper presents an analytic model of quantization for thin cylindrical Si-Nanowire MOSFETs by using a variational approach. The model is implemented into a surface potential like model. It is shown that results agree with the numerical simulations.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133612446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Self-aligned inversion channel In0.53Ga0.47As N-MOSFETs with ALD-Al2O3 and MBE-Al2O3/Ga2O3(Gd2O3) as gate dielectrics 以ALD-Al2O3和MBE-Al2O3/Ga2O3(Gd2O3)为栅极介质的自对准反转通道In0.53Ga0.47As n - mosfet
2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159329
H. Chiu, T. Lin, P. Chang, W. Lee, C. Chiang, J. Kwo, Y. Lin, S. Hsu, W. Tsai, M. Hong
{"title":"Self-aligned inversion channel In0.53Ga0.47As N-MOSFETs with ALD-Al2O3 and MBE-Al2O3/Ga2O3(Gd2O3) as gate dielectrics","authors":"H. Chiu, T. Lin, P. Chang, W. Lee, C. Chiang, J. Kwo, Y. Lin, S. Hsu, W. Tsai, M. Hong","doi":"10.1109/VTSA.2009.5159329","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159329","url":null,"abstract":"Self-aligned inversion-channel In<inf>0.53</inf>Ga<inf>0.47</inf>As n-MOSFETs with ex-situ atomic-layer-deposited Al<inf>2</inf>O<inf>3</inf> and in-situ ultra-high-vacuum deposited Al<inf>2</inf>O<inf>3</inf>/Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>) as gate dielectrics have been demonstrated. Both devices exhibit excellent DC characteristics, including high drain currents and transconductances. In addition, RF characteristics of both devices were analyzed; without using any isolation, non de-embedded current gain cutoff frequency (fT) and maximum oscillation frequency (f<inf>max</inf>) of ∼ 3.1 and 1.1 GHz (ALD-Al<inf>2</inf>O<inf>3</inf>) and of ∼ 17.9 and 11.2 GHz (MBE-Al<inf>2</inf>O<inf>3</inf>/Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>)), respectively, have been obtained.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124086408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The impact on device characteristics with STI formed by spin-on dielectric in high density NAND flash memory 高密度NAND快闪记忆体中自旋介电体形成STI对元件特性的影响
2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159268
W. Wong, J. J. Fan, J. Jiang, C. Huang, C. Chen, H. Chen, C. Hsu, R. Young, P. Wang, H. Fujita, H. Kobayashi
{"title":"The impact on device characteristics with STI formed by spin-on dielectric in high density NAND flash memory","authors":"W. Wong, J. J. Fan, J. Jiang, C. Huang, C. Chen, H. Chen, C. Hsu, R. Young, P. Wang, H. Fujita, H. Kobayashi","doi":"10.1109/VTSA.2009.5159268","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159268","url":null,"abstract":"The electrical impact from adopting spin-on dielectric (SOD) for shallow trench isolation is demonstrated in this paper. Although perfect STI gap filling and suppressed re-oxidation of tunneling oxide near the active area (AA) edge are achieved through SOD process, some unexpected side effects occur. In peripheral area, severe corner thinning of thick gate oxide and positive fixed charge inside STI are observed, leading to distorted transistor I–V characteristics and deteriorated junction/well isolation capability. They are attributed to the mechanical stress from volume shrinkage when SOD material is transformed into pure silicon dioxide. [1]","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115914606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Double patterning interactions with wafer processing, OPC and physical design flows 双图案与晶圆处理,OPC和物理设计流程的相互作用
2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159307
K. Lucas
{"title":"Double patterning interactions with wafer processing, OPC and physical design flows","authors":"K. Lucas","doi":"10.1109/VTSA.2009.5159307","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159307","url":null,"abstract":"In this work we study interactions of double patterning technology (DPT) with lithography, masks synthesis and physical design flows for the 22nm device node. DPT methods decompose the original design intent into two individual masking layers which are each patterned using single exposures and existing 193nm lithography tools. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step which will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons where required; and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals such as: reduce circuit area; minimize rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure symmetric wafer results; and create uniform wafer density for the individual patterning layers.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122327785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Overall operation considerations for a SONOS-based memory 基于sonos的内存的总体操作注意事项
2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159334
C. H. Lee, W. Tu, L. Chong, S. Gu, K.F. Chen, Y. J. Chen, J. Hsieh, I. Huang, N. Zous, T. Han, M. Chen, W. P. Lu, K. C. Chen, Tahui Wang, C.Y. Lu
{"title":"Overall operation considerations for a SONOS-based memory","authors":"C. H. Lee, W. Tu, L. Chong, S. Gu, K.F. Chen, Y. J. Chen, J. Hsieh, I. Huang, N. Zous, T. Han, M. Chen, W. P. Lu, K. C. Chen, Tahui Wang, C.Y. Lu","doi":"10.1109/VTSA.2009.5159334","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159334","url":null,"abstract":"Erase characteristics of a SONOS-based structure are emulated not only for n+-poly and p+-poly gates but also for TaN-gate+Al2O3 combination. By incorporating our previous studies, performances including program, erase, and read disturb can be reviewed for both SONOS and TANOS devices. Unsurprisingly, it is hard to satisfy all requirements by using a SONOS device. In a TANOS device, an optimal bottom oxide thickness can be specified with the consideration of the three factors simultaneously. Moreover, it is found that conventional extrapolation methodology is inadequate to predict the lifetime of a TANOS device and tends to under-estimate the tolerable read bias.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121079817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multi-level phase change memory using slow-quench operation: GST vs. GSST 使用慢淬操作的多级相变存储器:GST vs. GSST
2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159282
D. Chao, Frederick T. Chen, Y. Hsu, Wenhsing Liu, Chain-Ming Lee, Chih-Wei Chen, Weisu Chen, M. Kao, M. Tsai
{"title":"Multi-level phase change memory using slow-quench operation: GST vs. GSST","authors":"D. Chao, Frederick T. Chen, Y. Hsu, Wenhsing Liu, Chain-Ming Lee, Chih-Wei Chen, Weisu Chen, M. Kao, M. Tsai","doi":"10.1109/VTSA.2009.5159282","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159282","url":null,"abstract":"In this paper, we demonstrate the use of a slow-quench waveform for multi-level phase change memory operation and compare the use of Ge<inf>21</inf>Sn<inf>10</inf>Sb<inf>15</inf>Te<inf>54</inf> (GSST) and Ge<inf>2</inf>Sb<inf>2</inf>Te<inf>5</inf> (GST). A faster multilevel operation is possible with the use of GSST, owing to its faster crystallization speed","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115177138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
NGL Overview NGL概览》
2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-01 DOI: 10.1109/vtsa.2009.5159306
B. Lin
{"title":"NGL Overview","authors":"B. Lin","doi":"10.1109/vtsa.2009.5159306","DOIUrl":"https://doi.org/10.1109/vtsa.2009.5159306","url":null,"abstract":"ArF water-immersion lithography supports 1.35 NA or slightly higher but cannot reach the theoretical limit of 1.44 NA. It is increasing difficult to resolve half pitches below k1=(HP/λ)*NA=0.28, i.e. 40-nm half pitch.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134086598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Session 11 会议11
2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 1900-01-01 DOI: 10.1109/pccc.2004.1395182
W. G. Lotz
{"title":"Session 11","authors":"W. G. Lotz","doi":"10.1109/pccc.2004.1395182","DOIUrl":"https://doi.org/10.1109/pccc.2004.1395182","url":null,"abstract":"The session on high power, pulsed radio-frequency fields consisted of six papers that addressed issues of dosimetry, cellular effects, and thermophysiological effects that are associated with the radio-frequency (RF) signals used in nuclear magnetic resonance imaging (MRI) or spectroscopy (MRS). These papers provided a stimulating, insightful, up-to-date overview of this particular area of bioelectromagnetics. Four of the papers were concerned with theoretical dosimetry and employed numerical methods to predict the specific absorption rate (SAR) in the body during MRI. The other two papers were concerned with the biological responses to these fields in cells or in animals and humans where their effect on thermal physiology is of primary importance. The dosimetry papers included two presentations [(i) Gandhi and Chen and (ii) Grandolfo et a/ .] of research using numerical analysis of a complex, anatomically realistic model of the human body composed of several thousand individual cells or compartments (typically 1-1.5 cm in length). This modeling technique is known as the “impedance method” because each cell is characterized by its electrical impedance. Two other theoretical dosimetry papers [(i) Bottomley and Roemer and (ii) Boesiger ef al.] were based on numerical analyses of simpler geometric models of spheres and cylinders. Initial work in the field of dosimetry of MRI used the simpler geometric models, whereas the application of the impedance method to MRI is a new contribution. The individual papers discussed the assumptions, strengths, and weaknesses of each method. These dosimetry methods are directed toward the analysis of the primary known effect of radio-frequency exposure, namely, heating of tissues. The techniques must take into account or make assumptions for the many complex factors affecting the absorption of RF energy by the body, including frequency, variations in time and space of the intensity of the magnetic field, coupling efficiency between the R F coil and the body, duty cycle and waveform of the specific pulse sequence used in imaging, electrical properties of different tissues, geometry, and orientation of the body with respect to the polarity of the field. All of the authors deal with both average and local (or peak) S A R s for various MRI conditions. Considerations of local SARs in different regions of the body (e.g., skin) are the most difficult to determine and thus are the ones that received the most discussion. The impedance method has the capability to provide much more detailed information about internal current distribution and local S A R than the simpler geometric models. However, one of the points that stimulated the most discussion, in this session, was the difference of opinion over the significance of eddy currents in determining the SAR. Bottomley and Roemer presented challenging arguments","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116986195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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