2009 International Symposium on VLSI Technology, Systems, and Applications最新文献_第6页

Metal-oxide-semiconductor devices with UHV-Ga2O3(Gd2O3) on Ge(100) 在Ge(100)上具有UHV-Ga2O3(Gd2O3)的金属氧化物半导体器件

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159328

L. Chu, T. Lin, C. H. Lee, L. T. Tung, W. Lee, R. Chu, C. C. Chang, M. Hong, J. Kwo

引用次数: 0

Tri-gated poly-Si nanowire SONOS devices 三门控多晶硅纳米线SONOS器件

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159333

H. Hsu, T. Liu, Chuan-Ding Lin, Chiu Kuo-Jung, Tiao-Yuan Huang, Horng-Chih Lin

引用次数: 3

A new technique to extract the gate bias dependent s/d series resistance of sub-100nm MOSFETs 一种提取亚100nm mosfet栅极偏置相关s/d串联电阻的新技术

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159314

D. Fleury, A. Cros, G. Bidal, H. Brut, E. Josse, G. Ghibaudo

引用次数: 12

Nanoelectromechanical systems for ultra-low-power computing and VLSI 超低功耗计算和超大规模集成电路的纳米机电系统

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159286

P. Feng

{"title":"Nanoelectromechanical systems for ultra-low-power computing and VLSI","authors":"P. Feng","doi":"10.1109/VTSA.2009.5159286","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159286","url":null,"abstract":"Nanoscale devices with mechanical degrees of freedom offer compelling characteristics that make them very attractive for mechanical and quantum logic devices. As we are able to create nanoelectromechanical systems (NEMS) with unprecedented feature sizes, advanced complexity and functionality, and high yield and control (at wafer-scale), they become increasingly interesting for low-power logic and memory, as well as become more meaningful for VLSI. Partly this is driven by NEMS devices' unique merits such as exceptionally large on/off ratio, non-leakage, ultralow switching power, fast speed, and temperature insensitivity. In parallel, this is also an intriguing effort in the quest for the ultimately energy-efficient implementation of logic and computing. In this talk, I shall introduce the Caltech research effort towards these goals, including the recent demonstrations of several generic prototypes of nanoscale electromechanical switching devices, their characteristics and performance, progress on engineering such building blocks for NEMS-based logic and memory, all-mechanical and hybrid NEMS-CMOS, along with discussions and perspectives of technological promises and challenges.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132395370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reliability study of MANOS with and without a SiO2 buffer layer and BE-MANOS charge-trapping NAND flash devices 有和没有SiO2缓冲层的MANOS和BE-MANOS电荷捕获NAND闪存器件的可靠性研究

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159335

C.W. Liao, S. Lai, H. Lue, Ming-Jui Yang, C. Shen, Y. Lue, Yu-Fong Huang, J. Hsieh, Szu-Yu Wang, G. Luo, C. Chien, K. Hsieh, Rich Liu, Chih-Yuan Lu

{"title":"Reliability study of MANOS with and without a SiO2 buffer layer and BE-MANOS charge-trapping NAND flash devices","authors":"C.W. Liao, S. Lai, H. Lue, Ming-Jui Yang, C. Shen, Y. Lue, Yu-Fong Huang, J. Hsieh, Szu-Yu Wang, G. Luo, C. Chien, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/VTSA.2009.5159335","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159335","url":null,"abstract":"The reliability of MANOS devices with an oxide buffer layer (MAONOS) in between SiN trapping layer and high-K Al2O3 top dielectric is extensively studied. We conclude that the primary function of high-K Al2O3 is to suppress the gate electron injection during erase instead of increasing the P/E speed. As a result, inserting a buffer oxide only changes EOT but does not change the P/E mechanisms. On the other hand, the buffer oxide can greatly improve data retention by suppressing leakage through Al2O3. However, owing to the slow erase performances with a thick bottom oxide, both MANOS and MAONOS erase slowly and very high erase voltages must be used. Also, both MANOS and MAONOS devices show very fast endurance degradation below P/E≪10, which is inherent due to electron de-trapping mechanism. Moreover, the large erase voltage also causes severe degradation of tunnel oxide after many P/E cycling. To get both speed and reliability performances, it is necessary to introduce bandgap engineered tunneling barrier (BE-MANOS) to solve the fundamental problems of MANOS.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134296015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Impacts of NBTI on SRAM array with power gating structure NBTI对功率门控结构SRAM阵列的影响

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159298

Hao-I Yang, C. Chuang, W. Hwang

引用次数: 1

A novel Multi - Nitridation ONO interpoly dielectric (MN-ONO) for highly reliable and high performance NAND Flash memory 一种用于高可靠性和高性能NAND闪存的新型多氮化ONO插补电介质(MN-ONO)

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159280

C. H. Liu, Y. M. Lin, Y. Sakamoto, R. Yang, D. Yin, P. Chiang, H. Wei, C. Ho, S. H. Chen, H. Hwang, C. Hung, S. Pittikoun, S. Aritome

引用次数: 3

Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity 亚100nm高k金属栅极GeOI pmosfet性能:Ge通道取向和源注入速度的影响

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159331

C. Le Royer, A. Pouydebasque, K. Romanjek, V. Barral, M. Vinet, J. Hartmann, E. Augendre, H. Grampeix, L. Lachal, C. Tabone, B. Previtali, R. Truche, F. Allain

引用次数: 11

p-FinFETs with Al segregated NiSi/p+-Si source/drain contact junction for series resistance reduction 具有Al分离NiSi/p+-Si源极/漏极接触结的p- finfet，用于串联电阻降低

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159297

M. Sinha, Rinus Lee, S. N. Devi, G. Lo, E. Chor, Y. Yeo

引用次数: 0

Inversion-channel GaN MOSFET using atomic-layer-deposited Al2O3 as gate dielectric 用原子层沉积Al2O3作为栅极电介质的反转沟道GaN MOSFET

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159325

Y. Chang, W. Chang, H. Chiu, Y. H. Chang, L. T. Tung, C. H. Lee, M. Hong, J. Kwo, J. Hong, C. Tsai

引用次数: 7