2009 International Symposium on VLSI Technology, Systems, and Applications最新文献_第5页

Investigation of low frequency noise in uniaxial strained PMOSFETs 单轴应变pmosfet的低频噪声研究

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159301

J. Kuo, W. P. Chen, P. Su

引用次数: 3

The promise and implementation of three dimensional integration 三维一体化的承诺与实现

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159318

S. Iyer

{"title":"The promise and implementation of three dimensional integration","authors":"S. Iyer","doi":"10.1109/VTSA.2009.5159318","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159318","url":null,"abstract":"In many ways, three dimensional integration presents itself as a logical extension of planar monolithic integration - integration of additional function on the same die. Notwithstanding the remarkable advances in scaling we have witnessed over the last several decades, basic material limitations and lithography have slowed this trend down and the benefits of node to node migration need to be weighed against both technology development costs and complexity as well as the cost of design migration. Another consideration is die size which for high end applications such as high performance processors continues to increase well beyond the sweet spot dictated by yieldability, driven primarily by multiples cores and on-chip memory. Furthermore in such large die, long electrical paths cause significant delay and power draws. To address these limitations, three dimensional integration must be viewed beyond a simplistic packaging paradigm but rather as extension of silicon integration in the third dimension i.e., the introduction of low resistance, low inductance vertical interconnects between multiple active silicon strata that are co-designed in much the same way we design an SOC or ASIC today. This talk examines at the technology as it stands toady and the challenges going forward. These challenges include the development of fine pitch vertical interconnects and the degrees of integration they would permit. We will focus on the integration of three dimensional memory as the prototypical example of three dimensional integration and describe how these challenges are being met.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125456090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimizing tunnel FET performance - Impact of device structure, transistor dimensions and choice of material 优化隧道场效应管性能——器件结构、晶体管尺寸和材料选择的影响

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159285

J. Knoch

引用次数: 35

Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100K cycle endurance 带状工程隧道氧化物，用于改进tanos型闪存程序/擦除，具有良好的保留率和100K循环耐久性

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159337

D. Gilmer, N. Goel, S. Verma, Hokyung Park, Chanro Park, G. Bersuker, P. Kirsch, K. Saraswat, R. Jammy

{"title":"Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100K cycle endurance","authors":"D. Gilmer, N. Goel, S. Verma, Hokyung Park, Chanro Park, G. Bersuker, P. Kirsch, K. Saraswat, R. Jammy","doi":"10.1109/VTSA.2009.5159337","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159337","url":null,"abstract":"We demonstrate for the first time improved program, erase, and endurance for charge trap flash TaN-Al<inf>2</inf>O<inf>3</inf>-Si<inf>3</inf>N<inf>4</inf>-“Tunnel-oxide (TO)”-Si MOSFETs through band engineered tunnel oxides (BETO). Several high-K dielectrics (HfO<inf>2</inf>, HfSiO, Al<inf>2</inf>O<inf>3</inf>, Si<inf>3</inf>N<inf>4</inf>) and tunnel stack sequences (SiO<inf>2</inf>-high-k, SiO<inf>2</inf>-high-k-SiO<inf>2</inf>) are compared. New results are as follows: SiO<inf>2</inf>/Al<inf>2</inf>O<inf>3</inf> (OA) BE-TO and SiO<inf>2</inf>/Si<inf>3</inf>N<inf>4</inf>/SiO<inf>2</inf> (ONO) BE-TO ΔVth windows improve ≫300% vs. standard SiO<inf>2</inf>-TO. Both OA and ONO stacks endure P/E cycles to at least 100K cycles maintaining a window ≫4V. Results are consistent with a model based on high-k conduction/valence band offsets. Increased erase efficiency for BE-TO enables improved endurance without sacrificing P/E window due to lower P/E voltage stressing. These large, enduring windows are favorable for multi-level cell application and may extend TANOS flash beyond the 20nm node.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130244138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Optimization of the channel lateral strain profile for improved performance of multi-gate MOSFETs 改进多栅极mosfet性能的沟道横向应变分布图优化

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159319

L. De Michielis, K. E. Moselund, D. Bouvet, P. Dobrosz, S. Olsen, A. O'Neill, L. Lattanzio, M. Najmzadeh, L. Selmi, A. Ionescu

引用次数: 0

High-k/ metal-gate stack work-function tuning by rare-earth capping layers: Interface dipole or bulk charge? 稀土封盖层对高k/金属栅极叠加工作函数的调整:界面偶极子还是体电荷?

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159295

H. Yu, S. Chang, M. Aoulaiche, B. Kaczer, P. Absil, C. Adelmann, T. Hoffmann, S. Biesemans, C. Wann, Y. Mii

引用次数: 0

Investigation of static noise margin of Ultra-Thin-Body SOI SRAM cells in subthreshold region using analytical solution of poisson's equation 利用泊松方程的解析解研究超薄体SOI SRAM电池在亚阈值区域的静态噪声裕度

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159317

V. Hu, Yu-Sheng Wu, M. Fan, P. Su, C. Chuang

引用次数: 1

The standby power challenge: Wake-up receivers to the rescue 待机电源的挑战:唤醒接收器的救援

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159283

J. Rabaey

{"title":"The standby power challenge: Wake-up receivers to the rescue","authors":"J. Rabaey","doi":"10.1109/VTSA.2009.5159283","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159283","url":null,"abstract":"A large fraction of the average power dissipation of many modern multimedia components and mobile devices is spent in standby mode, scanning for potential input activity. Reducing the dissipation of the “always-on” components is essential to the realization of green devices. The common strategy is to duty-cycle the always-on components. While simple to implement, it comes at the expense of latency. A more effective approach that delivers both low standby-power and almost-zero latency is to exploit ultra low-power wake-up receivers. Combining innovative architectures with state-of-the-art CMOS and MEMS technologies, wake-up receivers have been built that consume less than 50 uW in on-mode. Their availability opens a whole new perspective on standby power management. On one end of the spectrum, they enable green devices to operate in a purely reactive mode, that is they are only turned on when input activity happens. On the other side, they allow for substantial improvements in existing communication protocols such as WiFi and Bluetooth. A number of examples will be presented in the talk. One important message that will emerge from the presentation however is that effective standby power management requires a system vision, and that the ad-hoc component-oriented approach of today will rarely be effective.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126683958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A VFB tunable Single Metal Single Dielectric approach using As I/I into TiN/HfO2 for 32nm node and beyond 采用As I/I进入TiN/HfO2的VFB可调谐单金属单介电介质方法，用于32nm及以上节点

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159289

J. Pétry, G. Boccardi, R. Singanamalla, C.S. Liu, K. Xiong, P. Escanes, J. Huguenin, J. Tseng, L. Van Nimwegen, F. Voogt, C. Bulle-lieuwma, M. Muller

引用次数: 5

Low current and voltage resistive switching memory device using novel Cu/Ta2O5/W structure 采用新型Cu/Ta2O5/W结构的低流压电阻开关存储器

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159279

S. Z. Rahaman, S. Maikap, C. Lin, T. Wu, Y. S. Chen, P. Tzeng, F. Chen, C. S. Lai, M. Kao, M. Tsai

引用次数: 4