The promise and implementation of three dimensional integration

S. Iyer
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Abstract

In many ways, three dimensional integration presents itself as a logical extension of planar monolithic integration - integration of additional function on the same die. Notwithstanding the remarkable advances in scaling we have witnessed over the last several decades, basic material limitations and lithography have slowed this trend down and the benefits of node to node migration need to be weighed against both technology development costs and complexity as well as the cost of design migration. Another consideration is die size which for high end applications such as high performance processors continues to increase well beyond the sweet spot dictated by yieldability, driven primarily by multiples cores and on-chip memory. Furthermore in such large die, long electrical paths cause significant delay and power draws. To address these limitations, three dimensional integration must be viewed beyond a simplistic packaging paradigm but rather as extension of silicon integration in the third dimension i.e., the introduction of low resistance, low inductance vertical interconnects between multiple active silicon strata that are co-designed in much the same way we design an SOC or ASIC today. This talk examines at the technology as it stands toady and the challenges going forward. These challenges include the development of fine pitch vertical interconnects and the degrees of integration they would permit. We will focus on the integration of three dimensional memory as the prototypical example of three dimensional integration and describe how these challenges are being met.
三维一体化的承诺与实现
在许多方面,三维集成表现为平面单片集成的逻辑扩展-在同一模具上集成附加功能。尽管在过去的几十年里,我们见证了可扩展性的显著进步,但基本的材料限制和光刻技术已经减缓了这一趋势,节点到节点迁移的好处需要与技术开发成本和复杂性以及设计迁移的成本进行权衡。另一个考虑因素是芯片尺寸,高端应用(如高性能处理器)的芯片尺寸继续增加,远远超出了可产性所决定的最佳点,主要是由多核和片上存储器驱动的。此外,在如此大的模具,长电路径造成显著的延迟和功耗。为了解决这些限制,三维集成必须超越简单的封装范例,而是作为第三维度硅集成的扩展,即在多个有源硅层之间引入低电阻,低电感垂直互连,这些互连与我们今天设计SOC或ASIC的方式非常相似。这次演讲将探讨当前的技术以及未来的挑战。这些挑战包括开发细间距垂直互连及其允许的集成程度。我们将把三维记忆的整合作为三维整合的典型例子,并描述如何应对这些挑战。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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