{"title":"优化隧道场效应管性能——器件结构、晶体管尺寸和材料选择的影响","authors":"J. Knoch","doi":"10.1109/VTSA.2009.5159285","DOIUrl":null,"url":null,"abstract":"In recent years tunnel FETs (TFETs) have attracted a great deal of attention [1–9]. The reason for this is that TFETs potentially allow beating the 60mV/dec limit and thus eventually enable lowering the power consumption of ICs. However, TFETs usually exhibit an onstate performance inferior to a conventional MOSFET. Moreover, in order to obtain a superior off-state TFETs must exhibit subthreshold swings substantially smaller than 60mV/dec over several orders of magnitude in current. In the present paper the impact of device structure, dimensions and the choice of material on the performance of TFETs will be discussed. In particular, the use of heterostructures and one-dimensional nanowires will be analyzed in detail.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":"{\"title\":\"Optimizing tunnel FET performance - Impact of device structure, transistor dimensions and choice of material\",\"authors\":\"J. Knoch\",\"doi\":\"10.1109/VTSA.2009.5159285\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In recent years tunnel FETs (TFETs) have attracted a great deal of attention [1–9]. The reason for this is that TFETs potentially allow beating the 60mV/dec limit and thus eventually enable lowering the power consumption of ICs. However, TFETs usually exhibit an onstate performance inferior to a conventional MOSFET. Moreover, in order to obtain a superior off-state TFETs must exhibit subthreshold swings substantially smaller than 60mV/dec over several orders of magnitude in current. In the present paper the impact of device structure, dimensions and the choice of material on the performance of TFETs will be discussed. In particular, the use of heterostructures and one-dimensional nanowires will be analyzed in detail.\",\"PeriodicalId\":309622,\"journal\":{\"name\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"35\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTSA.2009.5159285\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159285","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimizing tunnel FET performance - Impact of device structure, transistor dimensions and choice of material
In recent years tunnel FETs (TFETs) have attracted a great deal of attention [1–9]. The reason for this is that TFETs potentially allow beating the 60mV/dec limit and thus eventually enable lowering the power consumption of ICs. However, TFETs usually exhibit an onstate performance inferior to a conventional MOSFET. Moreover, in order to obtain a superior off-state TFETs must exhibit subthreshold swings substantially smaller than 60mV/dec over several orders of magnitude in current. In the present paper the impact of device structure, dimensions and the choice of material on the performance of TFETs will be discussed. In particular, the use of heterostructures and one-dimensional nanowires will be analyzed in detail.
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