D. Gilmer, N. Goel, S. Verma, Hokyung Park, Chanro Park, G. Bersuker, P. Kirsch, K. Saraswat, R. Jammy
{"title":"Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100K cycle endurance","authors":"D. Gilmer, N. Goel, S. Verma, Hokyung Park, Chanro Park, G. Bersuker, P. Kirsch, K. Saraswat, R. Jammy","doi":"10.1109/VTSA.2009.5159337","DOIUrl":null,"url":null,"abstract":"We demonstrate for the first time improved program, erase, and endurance for charge trap flash TaN-Al<inf>2</inf>O<inf>3</inf>-Si<inf>3</inf>N<inf>4</inf>-“Tunnel-oxide (TO)”-Si MOSFETs through band engineered tunnel oxides (BETO). Several high-K dielectrics (HfO<inf>2</inf>, HfSiO, Al<inf>2</inf>O<inf>3</inf>, Si<inf>3</inf>N<inf>4</inf>) and tunnel stack sequences (SiO<inf>2</inf>-high-k, SiO<inf>2</inf>-high-k-SiO<inf>2</inf>) are compared. New results are as follows: SiO<inf>2</inf>/Al<inf>2</inf>O<inf>3</inf> (OA) BE-TO and SiO<inf>2</inf>/Si<inf>3</inf>N<inf>4</inf>/SiO<inf>2</inf> (ONO) BE-TO ΔVth windows improve ≫300% vs. standard SiO<inf>2</inf>-TO. Both OA and ONO stacks endure P/E cycles to at least 100K cycles maintaining a window ≫4V. Results are consistent with a model based on high-k conduction/valence band offsets. Increased erase efficiency for BE-TO enables improved endurance without sacrificing P/E window due to lower P/E voltage stressing. These large, enduring windows are favorable for multi-level cell application and may extend TANOS flash beyond the 20nm node.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159337","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
We demonstrate for the first time improved program, erase, and endurance for charge trap flash TaN-Al2O3-Si3N4-“Tunnel-oxide (TO)”-Si MOSFETs through band engineered tunnel oxides (BETO). Several high-K dielectrics (HfO2, HfSiO, Al2O3, Si3N4) and tunnel stack sequences (SiO2-high-k, SiO2-high-k-SiO2) are compared. New results are as follows: SiO2/Al2O3 (OA) BE-TO and SiO2/Si3N4/SiO2 (ONO) BE-TO ΔVth windows improve ≫300% vs. standard SiO2-TO. Both OA and ONO stacks endure P/E cycles to at least 100K cycles maintaining a window ≫4V. Results are consistent with a model based on high-k conduction/valence band offsets. Increased erase efficiency for BE-TO enables improved endurance without sacrificing P/E window due to lower P/E voltage stressing. These large, enduring windows are favorable for multi-level cell application and may extend TANOS flash beyond the 20nm node.