M. Sinha, Rinus Lee, S. N. Devi, G. Lo, E. Chor, Y. Yeo
{"title":"具有Al分离NiSi/p+-Si源极/漏极接触结的p- finfet,用于串联电阻降低","authors":"M. Sinha, Rinus Lee, S. N. Devi, G. Lo, E. Chor, Y. Yeo","doi":"10.1109/VTSA.2009.5159297","DOIUrl":null,"url":null,"abstract":"This paper demonstrates the integration of Al segregated NiSi/p<sup>+</sup>-Si S/D contact junction in p-FinFETs for parasitic series resistance reduction. Al is introduced by ion implant into p<sup>+</sup> S/D region followed by nickel deposition and silicidation. Drive current enhancement of ∼15 % is achieved without any degradation of short channel effects. This is attributed to the lowering of Φ<inf>B</inf><sup>p</sup> of NiSi on p-Si from 0.4 eV to 0.12 eV with low Al dose of 2×10<sup>14</sup> atoms-cm<sup>−2</sup>, leading to lowering of contact resistance at NiSi/p<sup>+</sup>-Si S/D junction.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"p-FinFETs with Al segregated NiSi/p+-Si source/drain contact junction for series resistance reduction\",\"authors\":\"M. Sinha, Rinus Lee, S. N. Devi, G. Lo, E. Chor, Y. Yeo\",\"doi\":\"10.1109/VTSA.2009.5159297\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper demonstrates the integration of Al segregated NiSi/p<sup>+</sup>-Si S/D contact junction in p-FinFETs for parasitic series resistance reduction. Al is introduced by ion implant into p<sup>+</sup> S/D region followed by nickel deposition and silicidation. Drive current enhancement of ∼15 % is achieved without any degradation of short channel effects. This is attributed to the lowering of Φ<inf>B</inf><sup>p</sup> of NiSi on p-Si from 0.4 eV to 0.12 eV with low Al dose of 2×10<sup>14</sup> atoms-cm<sup>−2</sup>, leading to lowering of contact resistance at NiSi/p<sup>+</sup>-Si S/D junction.\",\"PeriodicalId\":309622,\"journal\":{\"name\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTSA.2009.5159297\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159297","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
p-FinFETs with Al segregated NiSi/p+-Si source/drain contact junction for series resistance reduction
This paper demonstrates the integration of Al segregated NiSi/p+-Si S/D contact junction in p-FinFETs for parasitic series resistance reduction. Al is introduced by ion implant into p+ S/D region followed by nickel deposition and silicidation. Drive current enhancement of ∼15 % is achieved without any degradation of short channel effects. This is attributed to the lowering of ΦBp of NiSi on p-Si from 0.4 eV to 0.12 eV with low Al dose of 2×1014 atoms-cm−2, leading to lowering of contact resistance at NiSi/p+-Si S/D junction.