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Proceedings of Eighth International Application Specific Integrated Circuits Conference最新文献

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Performance-driven MCM partitioning through an adaptive genetic algorithm 性能驱动的MCM分区通过自适应遗传算法
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580701
S. Raman, L. Patnaik
{"title":"Performance-driven MCM partitioning through an adaptive genetic algorithm","authors":"S. Raman, L. Patnaik","doi":"10.1109/ASIC.1995.580701","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580701","url":null,"abstract":"We present a novel genetic algorithm-based partitioning scheme for Multi-Chip Modules (MCMs) which integrates four performance constraints simultaneously: pin count, area, heat dissipation and timing. Experimental studies demonstrate the superiority of this method over deterministic Fiduccia Mattheyes (FM) algorithm and simulated annealing (SA) technique. The algorithm performs better than another such algorithm recently reported. The adaptive change of crossover and mutation probabilities results in better convergence.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133694603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Efficient timing analysis using constraint-guided critical path search 基于约束引导关键路径搜索的高效时序分析
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580734
C. Oh, M. R. Mercer
{"title":"Efficient timing analysis using constraint-guided critical path search","authors":"C. Oh, M. R. Mercer","doi":"10.1109/ASIC.1995.580734","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580734","url":null,"abstract":"This paper describes an efficient logic-level timing analysis approach that can provide an accurate delay estimate of a digital circuit which may have many long false paths. By using logic incompatibilities in a circuit as constraints for critical path search, the algorithm determines the longest sensitive path without explicit path enumeration. Since the number of false paths that can be implicitly eliminated is potentially exponential to the number of path constraints, performance improvement is significant.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125249206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design verification and emulation of a multichip high-speed GaAs RISC processor using soft-programmable logic 采用软可编程逻辑的多芯片高速GaAs RISC处理器的设计验证与仿真
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580706
S. Carlough, S. Steidl, A. N. Airapetian, A. Garg, C. Maier, P. Campbell, H.J. Greub, J. McDonald
{"title":"Design verification and emulation of a multichip high-speed GaAs RISC processor using soft-programmable logic","authors":"S. Carlough, S. Steidl, A. N. Airapetian, A. Garg, C. Maier, P. Campbell, H.J. Greub, J. McDonald","doi":"10.1109/ASIC.1995.580706","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580706","url":null,"abstract":"Soft-programmable logic is increasingly used to emulate and verify CMOS designs before fabrication. The F-RISC emulator uses this technology to emulate and verify a multichip GaAs RISC processor. An essential part of the F-RISC emulator is the mapping of the differential CML GaAs libraries to the Xilinx FPGA libraries. The emulator helped to detect several design errors.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128275906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An introduction to ATM technology and its applications 介绍ATM技术及其应用
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580758
D.C. Upp
{"title":"An introduction to ATM technology and its applications","authors":"D.C. Upp","doi":"10.1109/ASIC.1995.580758","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580758","url":null,"abstract":"ATM is a relatively new communications transport and switching technology. With ATM, all types of communications use short 53-byte \"cells\", constructed according to standardized rules. ATM networks are inherently capable of handling a virtually arbitrary mix of data, video, voice, and other communications at high and low rates. ATM technology has been in laboratories for years, and it has taken a shift in network requirements to bring it to its current level of interest. From the view of the internetworking industry, ATM is the best technology for building global, scaleable, manageable networks. At the same time the prospects for new services such as multimedia and Video-on-Demand are also well served by this common technology. ATM is now seeing application in LAN internetworking, with deployment in systems down to the home planned in the near future.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117324380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cost-effective process integration for a high performance 0.5 /spl mu/m CMOS logic device 具有成本效益的工艺集成，用于高性能0.5 /spl mu/m CMOS逻辑器件
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580697
Young-Wug Kim, Yongsik Kim, C. Oh, Bong-Seok Kim, J. Yoon, Bonggi Kim
{"title":"Cost-effective process integration for a high performance 0.5 /spl mu/m CMOS logic device","authors":"Young-Wug Kim, Yongsik Kim, C. Oh, Bong-Seok Kim, J. Yoon, Bonggi Kim","doi":"10.1109/ASIC.1995.580697","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580697","url":null,"abstract":"A high performance and cost-effective process for a 0.5 /spl mu/m CMOS logic device optimized for 3.3 V has been developed. To fill contacts and via holes, an in-situ Al reflow technique was employed instead of the high cost W-plug process. It was found that the in-situ Al reflow technique was very effective in improving the electrical properties and reliabilities of the multilevel interconnects. Quasi-global inter-metal-dielectric (IMD) planarization has been achieved by the COmbining PHOtoresist etchback and SOG etchback (COPHOS) process.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132471850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Full custom CMOS design and measurement of a video D/A converter 一个视频D/ a转换器的全定制CMOS设计和测量
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580731
J. Vanneuville, D. Gevaert, J. Sevenhans
{"title":"Full custom CMOS design and measurement of a video D/A converter","authors":"J. Vanneuville, D. Gevaert, J. Sevenhans","doi":"10.1109/ASIC.1995.580731","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580731","url":null,"abstract":"This paper describes the design and testing of a video 8-bit D/A converter, based on 63 binary non-weighted current cells, arranged in a 8/spl times/8 matrix for the 6 MSBs and 2 binary weighted current cells for the 2 LSBs. Each current cell is provided with a balanced output. Cascode transistors are used to increase the accuracy and speed of the switching current cells. The design has been simulated with HSPICE and processed in ES2 1.5 /spl mu/m CMOS technology. Measurement results are included.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131197884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VHDL macro library testing using BOAR emulation tool 使用BOAR仿真工具测试VHDL宏库
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580692
H. Hakkarainen, J. Isoaho
{"title":"VHDL macro library testing using BOAR emulation tool","authors":"H. Hakkarainen, J. Isoaho","doi":"10.1109/ASIC.1995.580692","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580692","url":null,"abstract":"In this paper, the testing of DSP and telecommunication macro library with an FPGA based emulation platform is introduced. The BOAR emulation system is targeted for animating accurately the modern ASIC and processor based systems, which make it also an efficient tool for validating the VHDL based macro components. By utilizing the emulator as a part of an ASIC design process, the testing time of the macros is reduced from several months to a few days, providing also huge savings in ASIC development costs and time.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131509765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A multichip module based RISC processor with programmable hardware 基于RISC处理器的多芯片模块，具有可编程硬件
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580695
M. Newell, W. Fang, Richard T. Johannesson, L. Alkalai
{"title":"A multichip module based RISC processor with programmable hardware","authors":"M. Newell, W. Fang, Richard T. Johannesson, L. Alkalai","doi":"10.1109/ASIC.1995.580695","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580695","url":null,"abstract":"A multichip module (MCM) based RISC processor with programmable hardware has been developed for the new era of miniaturized spacecraft required for NASA's \"faster, better, cheaper\" missions. The MCM based processor incorporates a complete 32-bit RISC computer including RAM, EEPROM and programmable hardware. This paper describes the system architecture and its associated MCM design and implementation. It also explores the architectural merits of including user programmable hardware.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121888396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A high-performance ROM compiler for 0.50 /spl mu/m and 0.36 /spl mu/m CMOS technologies 一个适用于0.50 /spl mu/m和0.36 /spl mu/m CMOS技术的高性能ROM编译器
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580751
R.L. Barry, J. Chickanosky, F. Masci, R. Piro, S.E. Oakland, M. Ouellette, D. W. Kemerer, M.R. Noack, W.C. Leipoid
{"title":"A high-performance ROM compiler for 0.50 /spl mu/m and 0.36 /spl mu/m CMOS technologies","authors":"R.L. Barry, J. Chickanosky, F. Masci, R. Piro, S.E. Oakland, M. Ouellette, D. W. Kemerer, M.R. Noack, W.C. Leipoid","doi":"10.1109/ASIC.1995.580751","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580751","url":null,"abstract":"A ROM compiler has been developed for use in IBM's 0.50 /spl mu/m and 0.36 /spl mu/m CMOS ASIC technologies. Late-personalized mask ROMs are generated for sizes from 512 bits to 256 K bits. The 0.50 /spl mu/m technology has a memory cell area of 6.40 /spl mu/m/sup 2/ with a typical access time of 6.0 ns, while the 0.36 /spl mu/m technology reduces memory cell area to 4.64 /spl mu/m/sup 2/ and has a 4.5 ns typical access time. The ROM includes DC and AC self-test.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129446662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Locally adaptive magnetic field detector 局部自适应磁场检测器
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580738
S. Hentschke, N. Reifshneider
{"title":"Locally adaptive magnetic field detector","authors":"S. Hentschke, N. Reifshneider","doi":"10.1109/ASIC.1995.580738","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580738","url":null,"abstract":"An electronically adjusting concept of a magnetic field sensor is presented on the basis of a new digital MAGFET cell array. Specially designed self calibrating basic cells detecting magnetic fields within an extremely small area in the sub-square-micron range are described. Cell arrays working in parallel mode will allow the adaptive recovering and reading of very small magnetic tracks defining the basic structure of future digital video heads.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121838044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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