具有成本效益的工艺集成，用于高性能0.5 /spl mu/m CMOS逻辑器件

Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI:10.1109/ASIC.1995.580697

Young-Wug Kim, Yongsik Kim, C. Oh, Bong-Seok Kim, J. Yoon, Bonggi Kim

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引用次数: 0

摘要

开发了一种用于优化3.3 V电压的0.5 /spl mu/m CMOS逻辑器件的高性能和经济高效的工艺。为了填充触点和通孔，采用原位铝回流技术代替了高成本的w塞工艺。结果表明，原位铝回流技术对提高多电平互连的电学性能和可靠性是非常有效的。采用光刻胶蚀刻与SOG蚀刻(COPHOS)相结合的方法实现了准全局金属间介电(IMD)平面化。

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Cost-effective process integration for a high performance 0.5 /spl mu/m CMOS logic device

A high performance and cost-effective process for a 0.5 /spl mu/m CMOS logic device optimized for 3.3 V has been developed. To fill contacts and via holes, an in-situ Al reflow technique was employed instead of the high cost W-plug process. It was found that the in-situ Al reflow technique was very effective in improving the electrical properties and reliabilities of the multilevel interconnects. Quasi-global inter-metal-dielectric (IMD) planarization has been achieved by the COmbining PHOtoresist etchback and SOG etchback (COPHOS) process.

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Proceedings of Eighth International Application Specific Integrated Circuits Conference

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