发布求助
文献互助 智能选刊 最新文献

Proceedings of Eighth International Application Specific Integrated Circuits Conference最新文献

筛选
英文 中文
A systematic approach to optimizing and verifying synthesized high-speed ASICs 一种优化和验证合成高速asic的系统方法
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-12-11 DOI: 10.1109/ASIC.1995.580724
Trevor C. Landon, M. H. Salinas, R. Klenke, J. Aylor, Sally A. McKee, K. L. Wright
{"title":"A systematic approach to optimizing and verifying synthesized high-speed ASICs","authors":"Trevor C. Landon, M. H. Salinas, R. Klenke, J. Aylor, Sally A. McKee, K. L. Wright","doi":"10.1109/ASIC.1995.580724","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580724","url":null,"abstract":"This paper describes the design process used in developing a Stream Memory Controller (SMC). The SMC can reorder processor-memory accesses dynamically to increase the effective memory bandwidth for vector operations. A 132-pin ASIC was implemented in static CMOS using a 0.75 /spl mu/m process and has been tested at 36 MHz.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"95 2 Suppl 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128461855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A comparison of FIR filter implementations based on two's complement and residue number arithmetic 基于二补数和余数算法的FIR滤波器实现比较
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580676
H. Ho, V. Szwarc, L. Desormeaux
{"title":"A comparison of FIR filter implementations based on two's complement and residue number arithmetic","authors":"H. Ho, V. Szwarc, L. Desormeaux","doi":"10.1109/ASIC.1995.580676","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580676","url":null,"abstract":"Two FIR filter designs based on residue number arithmetic (RNA) are presented and compared with a conventional design based on two's complement arithmetic (TCA). For the RNA based designs the arithmetic operations are implemented by means of small RAM and ROM look-up tables. The cascadeable and programmable ASICs, which can be configured as either 4-tap or 8-tap FIR filters, have been designed to the same functional specifications. The designs have been carried out using the MOSIS CMOSN 1.2 /spl mu/m technology, standard cell library, and memory compilers. Simulation and layout results for the selected FIR filter architectures indicate that the design based on TCA has the highest throughput and smallest area.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114676556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems 用于BiCMOS动态流水线数字逻辑VLSI系统的高速1.5 V时钟BiCMOS锁存器
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580739
J. Kuo, J. Lou, I.W. Su
{"title":"A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems","authors":"J. Kuo, J. Lou, I.W. Su","doi":"10.1109/ASIC.1995.580739","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580739","url":null,"abstract":"This paper presents a high-speed 1.5 V clocked BiCMOS dynamic latch, which is derived from a clocked CMOS dynamic latch and a BiCMOS logic gate using BiPMOS pull-down structure, and a bootstrapped pull-up structure, for BiCMOS dynamic pipelined digital logic systems. Based on the study, for driving a load capacitance of 2 pf, the 1.5 V clocked BiCMOS dynamic latch provides a 2.5/spl times/ improvement in switching time as compared to the clocked CMOS one.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122847178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Timing analysis models for gates and cells with bipolar-transistor output stages 双极晶体管输出级栅极和单元的时序分析模型
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580702
I. Tesu, L. Pileggi
{"title":"Timing analysis models for gates and cells with bipolar-transistor output stages","authors":"I. Tesu, L. Pileggi","doi":"10.1109/ASIC.1995.580702","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580702","url":null,"abstract":"A simple and efficient modeling technique for logic gates and cells with bipolar output stages is described. It permits the analysis of the gate and associated interconnect response waveforms, including the RC loading effects on the gate. The model decouples the gate problem into an intrinsic delay and a gate output impedance model which drives the RC load. The gate output impedance is modeled by a passive, linear, RLC circuit with the parameters specified as a function of an effective capacitance loading. Importantly, this output impedance model is shown to capture the oscillatory nature of emitter-follower output stages for BiCMOS and ECL gates. The passive nature of this impedance model makes it ideal for simulating the subsequent interconnect transient response using a model order reduction method such as moment matching.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129547640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Circuit techniques for standby mode/Iddq test compatible voltage comparators 待机模式/Iddq测试兼容电压比较器的电路技术
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580717
J. Caravella, D. Mietus, J.H. Quigley
{"title":"Circuit techniques for standby mode/Iddq test compatible voltage comparators","authors":"J. Caravella, D. Mietus, J.H. Quigley","doi":"10.1109/ASIC.1995.580717","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580717","url":null,"abstract":"This paper describes the means for IDDQ (quiescent supply current) testing of digital and mixed signal systems that contain analog circuits. A simple comparator design is presented that has been modified to be IDDQ test compatible. A by product of IDDQ test compatibility is a standby state that allows for a significant reduction in the IDDQ of the circuit, and an output data retention capability.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128423059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ALAS!: an analog layout assistant for matched and balanced CMOS components 唉!:用于匹配和平衡CMOS元件的模拟布局助手
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580729
J. Bruce, H. W. Li, M. Dallabetta
{"title":"ALAS!: an analog layout assistant for matched and balanced CMOS components","authors":"J. Bruce, H. W. Li, M. Dallabetta","doi":"10.1109/ASIC.1995.580729","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580729","url":null,"abstract":"Analog integrated circuits are more sensitive to process variations than their digital counterparts. This fact, along with the lack of analog standard cells, results in tedious layout of analog circuits. Layout techniques such as interdigitation can make key analog components less sensitive to process variation, but requires complicated and time consuming full-custom layout. This paper presents an analog layout assistant (ALAS!), that automatically generates matched and balanced CMOS component pairs with minimal input parameters from the user.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124713979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A performance-driven macro-block placer for architectural evaluation of ASIC designs 用于ASIC设计架构评估的性能驱动宏块放置器
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580721
Y. Mori, V. Moshnyaga, H. Onodera, K. Tamaru
{"title":"A performance-driven macro-block placer for architectural evaluation of ASIC designs","authors":"Y. Mori, V. Moshnyaga, H. Onodera, K. Tamaru","doi":"10.1109/ASIC.1995.580721","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580721","url":null,"abstract":"This paper presents a tool for generating a performance-driven placement from a netlist of Register-Transfer Level (RTL) blocks. Based on the modified force-directed algorithm, the tool chooses locations and orientations of the blocks such a way that to produce a compact area placement with minimum wiring delay along the critical path. Experiments show that our tool (1) provides solutions close to those generated manually, (2) is fast enough to be used in the inner loop of a program that synthesizes RTL structures from behavioral specifications and (3) ensures strong links between RTL synthesis and timing-driven layout so necessary for design of sub-micron ASICs.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123626982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
System design environment with synthesized blocks approach 用合成块方法设计系统环境
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580753
O. Bair, S. Soundararajan, A. Chen, M. Carbonara, C. Joly
{"title":"System design environment with synthesized blocks approach","authors":"O. Bair, S. Soundararajan, A. Chen, M. Carbonara, C. Joly","doi":"10.1109/ASIC.1995.580753","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580753","url":null,"abstract":"In this paper, we present a module generator capable of generating 14 different functional blocks with various options. Each block is pre-tested, pre-verified and optimized for speed and/or gate count. We also present a system design approach using the functional blocks created by this module generator. The module generator and the system design approach using the synthesized blocks it generates can increase designer productivity resulting in smaller, faster designs in less time.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131785068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A parallel 2 Gops/s image convolution processor with low I/O bandwidth 低输入/输出带宽的并行 2 Gops/s 图像卷积处理器
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580688
V. Öwall, M. Torkelson, Viktor Owall, M. Torkelson, Peter Egelberg
{"title":"A parallel 2 Gops/s image convolution processor with low I/O bandwidth","authors":"V. Öwall, M. Torkelson, Viktor Owall, M. Torkelson, Peter Egelberg","doi":"10.1109/ASIC.1995.580688","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580688","url":null,"abstract":"A customized image processor for real time convolution of an image has been developed. Image convolution requires an extensive amount of calculation capacity and I/O communication which is hard to sustain with standard processors in real time. Therefore, a customized processor has been designed with a tailored architecture. The processors have a total sustained calculation capacity of >2G arithmetic operations/s at 20 MHz clock frequency, surpassing that of TMS320C80 for this application due to the tailored architecture.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128450153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Deration of power dissipated in ASICs with temperature, process, and voltage variations 随着温度、工艺和电压的变化，asic中耗散的功率下降
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580669
H. Sarin
{"title":"Deration of power dissipated in ASICs with temperature, process, and voltage variations","authors":"H. Sarin","doi":"10.1109/ASIC.1995.580669","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580669","url":null,"abstract":"This paper presents a method to accurately derate power dissipated in ICs as temperature, process, and voltage are varied from the baseline conditions. Our cell-based power consumption model accounts for the waveform slope effects at the input of a gate, its output load, and logical state-dependencies, in terms of pre-characterized power coefficients. We further generalize this model to specify the temperature, process, and voltage sensitivities of each power coefficient. A representative subset of the library cells is first characterized at conditions varying from the baseline conditions. Since the standard deviation of scaling factors for each power coefficient is found to be within tolerance limits, for the remaining cells in that library we postulate the power deration factors based on the computed scaling factors. Results of our extensive power deration study for different logic cells verify our postulation. The power predicted by our method is within 5% of Spice results for temperature and voltage variations, and within 12% for process variations.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132844243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信