用于BiCMOS动态流水线数字逻辑VLSI系统的高速1.5 V时钟BiCMOS锁存器

Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI:10.1109/ASIC.1995.580739

J. Kuo, J. Lou, I.W. Su

{"title":"用于BiCMOS动态流水线数字逻辑VLSI系统的高速1.5 V时钟BiCMOS锁存器","authors":"J. Kuo, J. Lou, I.W. Su","doi":"10.1109/ASIC.1995.580739","DOIUrl":null,"url":null,"abstract":"This paper presents a high-speed 1.5 V clocked BiCMOS dynamic latch, which is derived from a clocked CMOS dynamic latch and a BiCMOS logic gate using BiPMOS pull-down structure, and a bootstrapped pull-up structure, for BiCMOS dynamic pipelined digital logic systems. Based on the study, for driving a load capacitance of 2 pf, the 1.5 V clocked BiCMOS dynamic latch provides a 2.5/spl times/ improvement in switching time as compared to the clocked CMOS one.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"146 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems\",\"authors\":\"J. Kuo, J. Lou, I.W. Su\",\"doi\":\"10.1109/ASIC.1995.580739\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a high-speed 1.5 V clocked BiCMOS dynamic latch, which is derived from a clocked CMOS dynamic latch and a BiCMOS logic gate using BiPMOS pull-down structure, and a bootstrapped pull-up structure, for BiCMOS dynamic pipelined digital logic systems. Based on the study, for driving a load capacitance of 2 pf, the 1.5 V clocked BiCMOS dynamic latch provides a 2.5/spl times/ improvement in switching time as compared to the clocked CMOS one.\",\"PeriodicalId\":307095,\"journal\":{\"name\":\"Proceedings of Eighth International Application Specific Integrated Circuits Conference\",\"volume\":\"146 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Eighth International Application Specific Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1995.580739\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1995.580739","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文提出了一种用于BiCMOS动态流水线数字逻辑系统的高速1.5 V时钟BiCMOS动态锁存器，该锁存器由时钟CMOS动态锁存器和BiCMOS逻辑门衍生而来，采用BiPMOS下拉结构和自引导上拉结构。基于研究，为驱动2pf的负载电容，与CMOS时钟锁存器相比，1.5 V时钟BiCMOS动态锁存器的开关时间提高了2.5倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems

This paper presents a high-speed 1.5 V clocked BiCMOS dynamic latch, which is derived from a clocked CMOS dynamic latch and a BiCMOS logic gate using BiPMOS pull-down structure, and a bootstrapped pull-up structure, for BiCMOS dynamic pipelined digital logic systems. Based on the study, for driving a load capacitance of 2 pf, the 1.5 V clocked BiCMOS dynamic latch provides a 2.5/spl times/ improvement in switching time as compared to the clocked CMOS one.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of Eighth International Application Specific Integrated Circuits Conference

自引率

0.00%

发文量