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Proceedings of Eighth International Application Specific Integrated Circuits Conference最新文献

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Vector-radix IDCT implementation for MPEG decoding 矢量基IDCT实现的MPEG解码
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580685
M. Zhou
{"title":"Vector-radix IDCT implementation for MPEG decoding","authors":"M. Zhou","doi":"10.1109/ASIC.1995.580685","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580685","url":null,"abstract":"This paper introduces a hardware architecture and VHDL implementation of a Vector-Radix DCT/IDCT algorithm. The architecture provides a true generic structure for both DCT and IDCT. For MPEG-1 video IDCT, it can run at a low frequency of 27 MHz to meet the data rate at SIF resolution with the additional capability of handling part of an inverse quantization task. For MPEG-2 at MP@ML, the IDCT can be carried out at 81 MHz clock rate. The 8/spl times/8 implementation can also be easily upgraded to handle any N/spl times/N transform of power of two.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123105680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Bridging the gap between ASIC behavioral and structural design 弥合ASIC行为设计和结构设计之间的差距
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580689
P. Jain
{"title":"Bridging the gap between ASIC behavioral and structural design","authors":"P. Jain","doi":"10.1109/ASIC.1995.580689","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580689","url":null,"abstract":"The methodology described in the paper bridges the gap between structural and behavioral design, raising the level of design capture, validation and optimization to the behavioral level. This methodology automates the current manual process of control design and enables IC designers to capture only the sources of control logic.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114449790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Maximal multiple fault coverage using single fault test sets 使用单个故障测试集实现最大的多个故障覆盖
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580720
A. Yousif, Jian Gu
{"title":"Maximal multiple fault coverage using single fault test sets","authors":"A. Yousif, Jian Gu","doi":"10.1109/ASIC.1995.580720","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580720","url":null,"abstract":"In this paper, an analysis based on the sensitization structure behavior in the existance of multiple faults for the general class of combinational circuits is presented. The analysis is based on partitioning the set of primary inputs into three subsets S/sub e/ (excitation set), S/sub p/ (persistency set), and S/sub c/ (control set). The problem of augmenting a single fault test set to obtain a maximal multiple fault coverage is formulated as the one of maximizing the number of primary inputs in the S/sub c/ set (or minimizing the number of primary inputs in S/sub p/) It is shown that this analysis can be used in extending single fault test sets in order to achieve a maximal multiple fault coverage. We have presented a procedure for augmenting any single fault test set. An experiment has been carried out on the 74LS181 ALU using twelve single fault test sets. It is shown that different fault classes can be covered using the procedure presented in this paper. A 100% double fault coverage for all the single fault tests is achieved.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122915272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An excursion into VHDL 对VHDL的介绍
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580754
J. Pick
{"title":"An excursion into VHDL","authors":"J. Pick","doi":"10.1109/ASIC.1995.580754","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580754","url":null,"abstract":"The complete VHDL journey known as The Excursion can be accomplished within eight hours. Upon its completion, the students will have encountered literally 90% of the VHDL language. The fundamental concepts of VHDL have consequently been mastered and the students are now prepared for the second part of the comprehensive course that the author has designed. The students can now view all subsequent course topics from a more mature perspective. They now understand how the various VHDL pieces fit together. Consequently, they can better grasp the overall significance of the modeling techniques and caveats presented in the remaining parts of the course. The flow of this complete four day VHDL training seminar is very popular with the students. Yet, as this paper shows, the overall success of this course depends very much on the in-depth journey that is conducted during the critical first day's lesson. This excursion into VHDL is much more than just a clever educational medium. It is also a very entertaining adventure in which the students directly interact with the real-world rhythm of VHDL.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128117712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
2.5 Gbit/s ATM switch chip set 2.5 Gbit/s ATM交换芯片组
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580708
P. Plaza, L. A. Merayo, J. C. Diaz, J. L. Conesa
{"title":"2.5 Gbit/s ATM switch chip set","authors":"P. Plaza, L. A. Merayo, J. C. Diaz, J. L. Conesa","doi":"10.1109/ASIC.1995.580708","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580708","url":null,"abstract":"The design and implementation of two application specific integrated circuits used to build an ATM switch are here described, the chip set is composed of: 1) the CMC which is an input/output processor of ATM cells implemented on a BiCMOS 0.7 micron technology; and 2) the ICM, a 0.7 micron CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131938081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Timed dependence flow graphs, an intermediate form for verified high-level synthesis 时间依赖流程图，一种经过验证的高级综合的中间形式
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580693
R. Chapman
{"title":"Timed dependence flow graphs, an intermediate form for verified high-level synthesis","authors":"R. Chapman","doi":"10.1109/ASIC.1995.580693","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580693","url":null,"abstract":"We present timed dependence flow graphs, an intermediate form for high-level synthesis from specifications written in behavioral hardware description languages. Timed dependence flow graphs express data, control, resource access, and timing dependences, and call be constructed in linear time from behavioral VHDL descriptions. We also present a formal execution semantics for timed dependence flow graphs, which we are using in verification of our high-level synthesis tools.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132396927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
18 channel 622 Mb/s CMOS receiver array for parallel optical interconnects 用于并行光互连的18通道622 Mb/s CMOS接收器阵列
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580713
K. Tu, T. Gabara, B. Levine, J. Wynn, N. Dutta, K. Monteleone
{"title":"18 channel 622 Mb/s CMOS receiver array for parallel optical interconnects","authors":"K. Tu, T. Gabara, B. Levine, J. Wynn, N. Dutta, K. Monteleone","doi":"10.1109/ASIC.1995.580713","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580713","url":null,"abstract":"An 18 channel 0.5 /spl mu/m CMOS optical receiver array operating at 622 Mb/s/ch with an aggregate throughput of 10 Gb/s has been fabricated. Experimental results indicate a BER of <10/sup -14/ at -10 dBm optical input for transmission through 30 meters of multimode fiber. Total DC power dissipation is less than 3 W.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125640054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Clock driven design method (CDDM) for deep sub-micron ASICs 深亚微米asic的时钟驱动设计方法(CDDM
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580723
T. Tanizawa, S. Kawahara
{"title":"Clock driven design method (CDDM) for deep sub-micron ASICs","authors":"T. Tanizawa, S. Kawahara","doi":"10.1109/ASIC.1995.580723","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580723","url":null,"abstract":"A newly developed CDDM achieves Concurrent Top-Down Design Flow. CDDM handles clock tree in the beginning of the design stage, and solves clock skews perfectly. It supplies accurate clock performance before main layout. A unique T-Bar/Star routing and FF-Virtual Placement were adopted to ensure 165 ps maximum clock skew for Fujitsu's 0.5 micron ASICs with no layout iteration.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129331950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Three-dimensional field-programmable gate arrays 三维现场可编程门阵列
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-03-04 DOI: 10.1109/ASIC.1995.580726
M. J. Alexander, J. Cohoon, J. L. Colflesh, J. Karro, G. Robins
{"title":"Three-dimensional field-programmable gate arrays","authors":"M. J. Alexander, J. Cohoon, J. L. Colflesh, J. Karro, G. Robins","doi":"10.1109/ASIC.1995.580726","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580726","url":null,"abstract":"Motivated by improving FPGA performance, we propose a new three-dimensional (3D) FPGA architecture, along with a fabrication methodology. We analyze the expected manufacturing yield, and raise several physical-design issues in the new 3D paradigm. Our techniques also have good implications for resource utilization, physical size, and power consumption.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116234145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 62
Digital filter ASIC for NASA deep space radio science receiver NASA深空无线电科学接收机数字滤波专用集成电路
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-03-01 DOI: 10.1109/ASIC.1995.580677
J. Kowalski, J. Berner
{"title":"Digital filter ASIC for NASA deep space radio science receiver","authors":"J. Kowalski, J. Berner","doi":"10.1109/ASIC.1995.580677","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580677","url":null,"abstract":"Implementation of an 80 MHz, 16-bit, multi-stage digital filter to decimate by 1600, providing a 50 kHz output with bandpass ripple of less than +/-0.1 dB is described. It uses two decimation by five units and six decimations by two executed by a single decimation by two unit. The six decimations by two consist of six halfband filters, five having 19-taps and one having 51-taps. Use of 16/spl times/16 register files for the digital delay lines and programmable coefficients enables implementation in the Vitesse 350 K gate array.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128027623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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