Digital filter ASIC for NASA deep space radio science receiver

Abstract

Implementation of an 80 MHz, 16-bit, multi-stage digital filter to decimate by 1600, providing a 50 kHz output with bandpass ripple of less than +/-0.1 dB is described. It uses two decimation by five units and six decimations by two executed by a single decimation by two unit. The six decimations by two consist of six halfband filters, five having 19-taps and one having 51-taps. Use of 16/spl times/16 register files for the digital delay lines and programmable coefficients enables implementation in the Vitesse 350 K gate array.