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Proceedings of Eighth International Application Specific Integrated Circuits Conference最新文献

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VHDL synthesis techniques and recommendations VHDL合成技术和建议
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580755
J. Pick
{"title":"VHDL synthesis techniques and recommendations","authors":"J. Pick","doi":"10.1109/ASIC.1995.580755","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580755","url":null,"abstract":"This tutorial presents a wide range of examples to emphasize that the synthesis of optimum hardware is tightly coupled to a designer's VHDL coding style. These examples also illustrate that a synthesis engineer must have a firm foundation in the VHDL language. Otherwise, any encountered compilation and simulation obstacles might hinder his/her synthesis project. Finally the observation is made that the synthesis engineer must also rely on his/her digital background to order to write VHDL models that will synthesize into optimum hardware.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122446443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A high-bandwidth voltage controlled oscillator (VCO) with a frequency-multiplied/divided range of 0.25-20 GHz implemented in a GaAs HBT process 在GaAs HBT工艺中实现了一种乘/分频率范围为0.25-20 GHz的高带宽压控振荡器(VCO)
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580679
P. Campbell, H. Greub, A. Garg, S. Steidl, C. Maier, S. Carlough, J. McDonald
{"title":"A high-bandwidth voltage controlled oscillator (VCO) with a frequency-multiplied/divided range of 0.25-20 GHz implemented in a GaAs HBT process","authors":"P. Campbell, H. Greub, A. Garg, S. Steidl, C. Maier, S. Carlough, J. McDonald","doi":"10.1109/ASIC.1995.580679","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580679","url":null,"abstract":"A high speed voltage-controlled oscillator (VCO) bas been developed using 50 GHz GaAs-AlGaAs HBTs which can generate differential signals in the range of 0.25-20 GHz. The design process was focused on producing a layout with highly-matched parasitic capacitance by exploiting the high degree of symmetry present in differential circuits. The system design and cell layout techniques are described in detail using examples from the VCO. The operation of the VCO is also discussed along with design tradeoffs.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126657806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multiple fault simulation with random and clustered fault injection 基于随机和聚类故障注入的多故障仿真
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580718
C. Stroud, C. A. Ryan
{"title":"Multiple fault simulation with random and clustered fault injection","authors":"C. Stroud, C. A. Ryan","doi":"10.1109/ASIC.1995.580718","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580718","url":null,"abstract":"A logic and fault simulator is described which provides gate-level multiple stuck-at fault simulation as well as traditional single stuck-at fault simulation. The multiple fault simulation supports random and clustered fault injection for the verification and evaluation of multiple fault detection capabilities of test vector sets as well as fault and defect-tolerant design techniques.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127516826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
VHDL and silicon compiler experience in the advanced processor interface unit ASIC design 有VHDL和硅编译器高级处理器接口单元ASIC设计经验
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580742
K. Chang, H. Le, C. Ling, D. Lin
{"title":"VHDL and silicon compiler experience in the advanced processor interface unit ASIC design","authors":"K. Chang, H. Le, C. Ling, D. Lin","doi":"10.1109/ASIC.1995.580742","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580742","url":null,"abstract":"This paper summarizes the process of designing an advanced processor interface unit (APIU) ASIC using VHDL simulation, synthesis, and silicon compilation. Problems and areas for improvements in the interface between different CAD tool environments are addressed. VHDL entity and hierarchy partition guidelines are discussed with examples.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127560853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Re-engineering ASIC design with LPGAs 用lpga重新设计ASIC
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580682
M. Janai
{"title":"Re-engineering ASIC design with LPGAs","authors":"M. Janai","doi":"10.1109/ASIC.1995.580682","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580682","url":null,"abstract":"The availability of Laser Programmable Gate-Arrays (LPGAs) of over 100k gates which can be economically produced within a few hours simplifies considerably the design cycle and shortens the time-to-market of systems incorporating gate arrays. The technological background and architecture of LPGAs, and the methodology of transfer from design to volume production are described.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116554561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CCD camera design and ASIC applications CCD相机的设计和ASIC的应用
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580757
W. Chan
{"title":"CCD camera design and ASIC applications","authors":"W. Chan","doi":"10.1109/ASIC.1995.580757","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580757","url":null,"abstract":"A guideline for the design of a CCD camera is presented. A generalized camera system model contains the following key components: optical lens, CCD sensor, A/D converter, digital signal processor, and system controller. The characteristics of a CCD sensor, which dominates the system's performance, is explained in-depth. The main parameters for system performance evaluation are noise, resolution, and modulation transfer function. Currently, to develop a digital signal processing ASIC is still a major effort in the CCD camera development. The general functions of a DSP/ASIC, which was developed in our laboratory, are described.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131358346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Testability controlled physical design of vertically stacked integrated circuits 垂直堆叠集成电路的可测试性控制物理设计
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580725
M. Reber, A. Kirsch
{"title":"Testability controlled physical design of vertically stacked integrated circuits","authors":"M. Reber, A. Kirsch","doi":"10.1109/ASIC.1995.580725","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580725","url":null,"abstract":"Vertical integration technology is expected to provide several advantages, such as high packaging density, parallel processing, high speed operation and an improved reliability. Basic design aspects for vertically stacked integrated circuits are discussed in this paper. A novel partitioning method for vertically stacked integrated circuits (VIC) will be proposed which generates testable circuit partitions. Generated circuit layouts of partitioned MCNC benchmark circuits demonstrate the superiority of 3-D circuit layouts over planar circuit layouts especially for increased circuit sizes.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132741013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-level analog synthesis using signal flow graph transformations 使用信号流图变换的高级模拟合成
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580750
R.S. Guindi, M. Elmasry
{"title":"High-level analog synthesis using signal flow graph transformations","authors":"R.S. Guindi, M. Elmasry","doi":"10.1109/ASIC.1995.580750","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580750","url":null,"abstract":"A high-level top-down analog synthesis methodology is presented. It translates an initial signal flow graph representation of a transfer function into an architecture made of interconnected analog primitives. Constraints are imposed on the primitive weights and interconnections to ensure realizability. Transformations that generate realisable architectures are presented and illustrated through examples.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129894361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Decompositional logic synthesis approach for look up table FPGAs 查找表fpga的分解逻辑综合方法
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580748
F.A.M. Volf, L. Józwiak
{"title":"Decompositional logic synthesis approach for look up table FPGAs","authors":"F.A.M. Volf, L. Józwiak","doi":"10.1109/ASIC.1995.580748","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580748","url":null,"abstract":"In this paper, a technology driven logic synthesis approach for look up table FPGAs is presented. Decomposition and bottom-up construction are the key concepts of this approach. By using functionally complete compact modeling with set systems, technology mapping is trivial. The method offers correctness by construction and easy post-synthesis verification and uses a multiple criteria search algorithm for constructing near optimal solutions.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131137548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
VHDL code automatic generation for repetitive designs VHDL代码自动生成，用于重复设计
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580690
S. Gastaldello, A. Lometti, G. Traverso
{"title":"VHDL code automatic generation for repetitive designs","authors":"S. Gastaldello, A. Lometti, G. Traverso","doi":"10.1109/ASIC.1995.580690","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580690","url":null,"abstract":"The introduction of VHDL in ASIC design has radically changed perspectives for HW designers. As a matter of fact ASIC design characteristics are becoming more and more similar to those typical of SW design. So, the application of SW methodologies to HW VHDL design can, in different cases, open unusual possibilities and give great improvement. In this paper a new design approach is described for circuits characterised by a high degree of recurrence in constituting parts, consisting in VHDL code generation starting from high level description in a suitable language.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134536365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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