VHDL synthesis techniques and recommendations

Abstract

This tutorial presents a wide range of examples to emphasize that the synthesis of optimum hardware is tightly coupled to a designer's VHDL coding style. These examples also illustrate that a synthesis engineer must have a firm foundation in the VHDL language. Otherwise, any encountered compilation and simulation obstacles might hinder his/her synthesis project. Finally the observation is made that the synthesis engineer must also rely on his/her digital background to order to write VHDL models that will synthesize into optimum hardware.