{"title":"基于随机和聚类故障注入的多故障仿真","authors":"C. Stroud, C. A. Ryan","doi":"10.1109/ASIC.1995.580718","DOIUrl":null,"url":null,"abstract":"A logic and fault simulator is described which provides gate-level multiple stuck-at fault simulation as well as traditional single stuck-at fault simulation. The multiple fault simulation supports random and clustered fault injection for the verification and evaluation of multiple fault detection capabilities of test vector sets as well as fault and defect-tolerant design techniques.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Multiple fault simulation with random and clustered fault injection\",\"authors\":\"C. Stroud, C. A. Ryan\",\"doi\":\"10.1109/ASIC.1995.580718\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A logic and fault simulator is described which provides gate-level multiple stuck-at fault simulation as well as traditional single stuck-at fault simulation. The multiple fault simulation supports random and clustered fault injection for the verification and evaluation of multiple fault detection capabilities of test vector sets as well as fault and defect-tolerant design techniques.\",\"PeriodicalId\":307095,\"journal\":{\"name\":\"Proceedings of Eighth International Application Specific Integrated Circuits Conference\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Eighth International Application Specific Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1995.580718\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1995.580718","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multiple fault simulation with random and clustered fault injection
A logic and fault simulator is described which provides gate-level multiple stuck-at fault simulation as well as traditional single stuck-at fault simulation. The multiple fault simulation supports random and clustered fault injection for the verification and evaluation of multiple fault detection capabilities of test vector sets as well as fault and defect-tolerant design techniques.