Decompositional logic synthesis approach for look up table FPGAs

Abstract

In this paper, a technology driven logic synthesis approach for look up table FPGAs is presented. Decomposition and bottom-up construction are the key concepts of this approach. By using functionally complete compact modeling with set systems, technology mapping is trivial. The method offers correctness by construction and easy post-synthesis verification and uses a multiple criteria search algorithm for constructing near optimal solutions.