2.5 Gbit/s ATM交换芯片组

Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI:10.1109/ASIC.1995.580708

P. Plaza, L. A. Merayo, J. C. Diaz, J. L. Conesa

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引用次数: 1

摘要

本文介绍了用于构建ATM交换机的两种专用集成电路的设计和实现，该芯片组由以下几个部分组成:1)CMC是基于BiCMOS 0.7微米技术实现的ATM单元的输入/输出处理器;2) ICM，一个0.7微米的CMOS IC，在68兆赫执行单元切换。ATM交换机利用并行性和分段来执行每个输入/输出2.5 Gb/s的交换。

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2.5 Gbit/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are here described, the chip set is composed of: 1) the CMC which is an input/output processor of ATM cells implemented on a BiCMOS 0.7 micron technology; and 2) the ICM, a 0.7 micron CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output.

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Proceedings of Eighth International Application Specific Integrated Circuits Conference

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