三维现场可编程门阵列

Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-03-04 DOI:10.1109/ASIC.1995.580726

M. J. Alexander, J. Cohoon, J. L. Colflesh, J. Karro, G. Robins

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引用次数: 62

摘要

为了提高FPGA的性能，我们提出了一种新的三维(3D) FPGA架构，以及一种制造方法。我们分析了预期的制造良率，并在新的3D范例中提出了几个物理设计问题。我们的技术对资源利用、物理大小和功耗也有很好的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Three-dimensional field-programmable gate arrays

Motivated by improving FPGA performance, we propose a new three-dimensional (3D) FPGA architecture, along with a fabrication methodology. We analyze the expected manufacturing yield, and raise several physical-design issues in the new 3D paradigm. Our techniques also have good implications for resource utilization, physical size, and power consumption.

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Proceedings of Eighth International Application Specific Integrated Circuits Conference

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