深亚微米asic的时钟驱动设计方法(CDDM

Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI:10.1109/ASIC.1995.580723

T. Tanizawa, S. Kawahara

{"title":"深亚微米asic的时钟驱动设计方法(CDDM","authors":"T. Tanizawa, S. Kawahara","doi":"10.1109/ASIC.1995.580723","DOIUrl":null,"url":null,"abstract":"A newly developed CDDM achieves Concurrent Top-Down Design Flow. CDDM handles clock tree in the beginning of the design stage, and solves clock skews perfectly. It supplies accurate clock performance before main layout. A unique T-Bar/Star routing and FF-Virtual Placement were adopted to ensure 165 ps maximum clock skew for Fujitsu's 0.5 micron ASICs with no layout iteration.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Clock driven design method (CDDM) for deep sub-micron ASICs\",\"authors\":\"T. Tanizawa, S. Kawahara\",\"doi\":\"10.1109/ASIC.1995.580723\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A newly developed CDDM achieves Concurrent Top-Down Design Flow. CDDM handles clock tree in the beginning of the design stage, and solves clock skews perfectly. It supplies accurate clock performance before main layout. A unique T-Bar/Star routing and FF-Virtual Placement were adopted to ensure 165 ps maximum clock skew for Fujitsu's 0.5 micron ASICs with no layout iteration.\",\"PeriodicalId\":307095,\"journal\":{\"name\":\"Proceedings of Eighth International Application Specific Integrated Circuits Conference\",\"volume\":\"77 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Eighth International Application Specific Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1995.580723\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1995.580723","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

新开发的CDDM实现了并发的自顶向下设计流程。CDDM在设计初期就处理了时钟树，很好地解决了时钟偏差。它在主布局前提供精确的时钟性能。采用独特的T-Bar/Star路由和FF-Virtual Placement，确保富士通0.5微米asic的最大时钟偏差为165 ps，无需布局迭代。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Clock driven design method (CDDM) for deep sub-micron ASICs

A newly developed CDDM achieves Concurrent Top-Down Design Flow. CDDM handles clock tree in the beginning of the design stage, and solves clock skews perfectly. It supplies accurate clock performance before main layout. A unique T-Bar/Star routing and FF-Virtual Placement were adopted to ensure 165 ps maximum clock skew for Fujitsu's 0.5 micron ASICs with no layout iteration.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of Eighth International Application Specific Integrated Circuits Conference

自引率

0.00%

发文量