A systematic approach to optimizing and verifying synthesized high-speed ASICs

Abstract

This paper describes the design process used in developing a Stream Memory Controller (SMC). The SMC can reorder processor-memory accesses dynamically to increase the effective memory bandwidth for vector operations. A 132-pin ASIC was implemented in static CMOS using a 0.75 /spl mu/m process and has been tested at 36 MHz.