A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems

Abstract

This paper presents a high-speed 1.5 V clocked BiCMOS dynamic latch, which is derived from a clocked CMOS dynamic latch and a BiCMOS logic gate using BiPMOS pull-down structure, and a bootstrapped pull-up structure, for BiCMOS dynamic pipelined digital logic systems. Based on the study, for driving a load capacitance of 2 pf, the 1.5 V clocked BiCMOS dynamic latch provides a 2.5/spl times/ improvement in switching time as compared to the clocked CMOS one.