双极晶体管输出级栅极和单元的时序分析模型

I. Tesu, L. Pileggi
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引用次数: 1

摘要

描述了一种简单有效的逻辑门和具有双极输出级的单元建模技术。它允许分析栅极和相关的互连响应波形,包括RC加载对栅极的影响。该模型将栅极问题解耦为一个固有延迟和一个驱动RC负载的栅极输出阻抗模型。门输出阻抗由无源线性RLC电路建模,其参数指定为有效电容负载的函数。重要的是,该输出阻抗模型被证明可以捕获BiCMOS和ECL门的发射器-从动器输出级的振荡性质。该阻抗模型的无源特性使其非常适合使用模型降阶方法(如矩匹配)模拟后续的互连瞬态响应。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Timing analysis models for gates and cells with bipolar-transistor output stages
A simple and efficient modeling technique for logic gates and cells with bipolar output stages is described. It permits the analysis of the gate and associated interconnect response waveforms, including the RC loading effects on the gate. The model decouples the gate problem into an intrinsic delay and a gate output impedance model which drives the RC load. The gate output impedance is modeled by a passive, linear, RLC circuit with the parameters specified as a function of an effective capacitance loading. Importantly, this output impedance model is shown to capture the oscillatory nature of emitter-follower output stages for BiCMOS and ECL gates. The passive nature of this impedance model makes it ideal for simulating the subsequent interconnect transient response using a model order reduction method such as moment matching.
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