一种优化和验证合成高速asic的系统方法

Trevor C. Landon, M. H. Salinas, R. Klenke, J. Aylor, Sally A. McKee, K. L. Wright
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引用次数: 2

摘要

本文介绍了流存储器控制器(SMC)的设计过程。SMC可以动态地重新排序处理器-存储器访问,以增加矢量操作的有效存储器带宽。采用0.75 /spl mu/m工艺在静态CMOS中实现了132引脚ASIC,并在36 MHz下进行了测试。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A systematic approach to optimizing and verifying synthesized high-speed ASICs
This paper describes the design process used in developing a Stream Memory Controller (SMC). The SMC can reorder processor-memory accesses dynamically to increase the effective memory bandwidth for vector operations. A 132-pin ASIC was implemented in static CMOS using a 0.75 /spl mu/m process and has been tested at 36 MHz.
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