Timing analysis models for gates and cells with bipolar-transistor output stages

Abstract

A simple and efficient modeling technique for logic gates and cells with bipolar output stages is described. It permits the analysis of the gate and associated interconnect response waveforms, including the RC loading effects on the gate. The model decouples the gate problem into an intrinsic delay and a gate output impedance model which drives the RC load. The gate output impedance is modeled by a passive, linear, RLC circuit with the parameters specified as a function of an effective capacitance loading. Importantly, this output impedance model is shown to capture the oscillatory nature of emitter-follower output stages for BiCMOS and ECL gates. The passive nature of this impedance model makes it ideal for simulating the subsequent interconnect transient response using a model order reduction method such as moment matching.