待机模式/Iddq测试兼容电压比较器的电路技术

J. Caravella, D. Mietus, J.H. Quigley
{"title":"待机模式/Iddq测试兼容电压比较器的电路技术","authors":"J. Caravella, D. Mietus, J.H. Quigley","doi":"10.1109/ASIC.1995.580717","DOIUrl":null,"url":null,"abstract":"This paper describes the means for IDDQ (quiescent supply current) testing of digital and mixed signal systems that contain analog circuits. A simple comparator design is presented that has been modified to be IDDQ test compatible. A by product of IDDQ test compatibility is a standby state that allows for a significant reduction in the IDDQ of the circuit, and an output data retention capability.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Circuit techniques for standby mode/Iddq test compatible voltage comparators\",\"authors\":\"J. Caravella, D. Mietus, J.H. Quigley\",\"doi\":\"10.1109/ASIC.1995.580717\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the means for IDDQ (quiescent supply current) testing of digital and mixed signal systems that contain analog circuits. A simple comparator design is presented that has been modified to be IDDQ test compatible. A by product of IDDQ test compatibility is a standby state that allows for a significant reduction in the IDDQ of the circuit, and an output data retention capability.\",\"PeriodicalId\":307095,\"journal\":{\"name\":\"Proceedings of Eighth International Application Specific Integrated Circuits Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Eighth International Application Specific Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1995.580717\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1995.580717","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

本文介绍了包含模拟电路的数字和混合信号系统的静态电源电流测试方法。提出了一种简单的比较器设计,并对其进行了修改,使其与IDDQ测试兼容。IDDQ测试兼容性的副产品是待机状态,该状态允许显著降低电路的IDDQ,并具有输出数据保留能力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Circuit techniques for standby mode/Iddq test compatible voltage comparators
This paper describes the means for IDDQ (quiescent supply current) testing of digital and mixed signal systems that contain analog circuits. A simple comparator design is presented that has been modified to be IDDQ test compatible. A by product of IDDQ test compatibility is a standby state that allows for a significant reduction in the IDDQ of the circuit, and an output data retention capability.
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