一个适用于0.50 /spl mu/m和0.36 /spl mu/m CMOS技术的高性能ROM编译器

Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI:10.1109/ASIC.1995.580751

R.L. Barry, J. Chickanosky, F. Masci, R. Piro, S.E. Oakland, M. Ouellette, D. W. Kemerer, M.R. Noack, W.C. Leipoid

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引用次数: 0

摘要

已经开发出用于IBM的0.50 /spl mu/m和0.36 /spl mu/m CMOS ASIC技术的ROM编译器。后期个性化掩码rom的大小从512位到256k位不等。0.50 /spl mu/m技术的存储单元面积为6.40 /spl mu/m/sup 2/，典型访问时间为6.0 ns，而0.36 /spl mu/m/sup 2/技术的存储单元面积为4.64 /spl mu/m/sup 2/，典型访问时间为4.5 ns。ROM包括直流自检和交流自检。

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A high-performance ROM compiler for 0.50 /spl mu/m and 0.36 /spl mu/m CMOS technologies

A ROM compiler has been developed for use in IBM's 0.50 /spl mu/m and 0.36 /spl mu/m CMOS ASIC technologies. Late-personalized mask ROMs are generated for sizes from 512 bits to 256 K bits. The 0.50 /spl mu/m technology has a memory cell area of 6.40 /spl mu/m/sup 2/ with a typical access time of 6.0 ns, while the 0.36 /spl mu/m technology reduces memory cell area to 4.64 /spl mu/m/sup 2/ and has a 4.5 ns typical access time. The ROM includes DC and AC self-test.

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Proceedings of Eighth International Application Specific Integrated Circuits Conference

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