A high-performance ROM compiler for 0.50 /spl mu/m and 0.36 /spl mu/m CMOS technologies

Abstract

A ROM compiler has been developed for use in IBM's 0.50 /spl mu/m and 0.36 /spl mu/m CMOS ASIC technologies. Late-personalized mask ROMs are generated for sizes from 512 bits to 256 K bits. The 0.50 /spl mu/m technology has a memory cell area of 6.40 /spl mu/m/sup 2/ with a typical access time of 6.0 ns, while the 0.36 /spl mu/m technology reduces memory cell area to 4.64 /spl mu/m/sup 2/ and has a 4.5 ns typical access time. The ROM includes DC and AC self-test.