M. Newell, W. Fang, Richard T. Johannesson, L. Alkalai
{"title":"基于RISC处理器的多芯片模块,具有可编程硬件","authors":"M. Newell, W. Fang, Richard T. Johannesson, L. Alkalai","doi":"10.1109/ASIC.1995.580695","DOIUrl":null,"url":null,"abstract":"A multichip module (MCM) based RISC processor with programmable hardware has been developed for the new era of miniaturized spacecraft required for NASA's \"faster, better, cheaper\" missions. The MCM based processor incorporates a complete 32-bit RISC computer including RAM, EEPROM and programmable hardware. This paper describes the system architecture and its associated MCM design and implementation. It also explores the architectural merits of including user programmable hardware.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A multichip module based RISC processor with programmable hardware\",\"authors\":\"M. Newell, W. Fang, Richard T. Johannesson, L. Alkalai\",\"doi\":\"10.1109/ASIC.1995.580695\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A multichip module (MCM) based RISC processor with programmable hardware has been developed for the new era of miniaturized spacecraft required for NASA's \\\"faster, better, cheaper\\\" missions. The MCM based processor incorporates a complete 32-bit RISC computer including RAM, EEPROM and programmable hardware. This paper describes the system architecture and its associated MCM design and implementation. It also explores the architectural merits of including user programmable hardware.\",\"PeriodicalId\":307095,\"journal\":{\"name\":\"Proceedings of Eighth International Application Specific Integrated Circuits Conference\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Eighth International Application Specific Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1995.580695\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1995.580695","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A multichip module based RISC processor with programmable hardware
A multichip module (MCM) based RISC processor with programmable hardware has been developed for the new era of miniaturized spacecraft required for NASA's "faster, better, cheaper" missions. The MCM based processor incorporates a complete 32-bit RISC computer including RAM, EEPROM and programmable hardware. This paper describes the system architecture and its associated MCM design and implementation. It also explores the architectural merits of including user programmable hardware.