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Proceedings of Eighth International Application Specific Integrated Circuits Conference最新文献

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An error correction-free 10-bit 5 MHz CMOS embedded subranging A/D converter with novel bisection MSB comparators 一种无纠错的10位5mhz CMOS嵌入式分位A/D转换器，带有新型对分MSB比较器
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580728
P. Hsu, Tien-Yu Wu, Chung-Yu Wu
{"title":"An error correction-free 10-bit 5 MHz CMOS embedded subranging A/D converter with novel bisection MSB comparators","authors":"P. Hsu, Tien-Yu Wu, Chung-Yu Wu","doi":"10.1109/ASIC.1995.580728","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580728","url":null,"abstract":"This paper describes a novel embedded subranging type 10-bit 5 MHz CMOS error correction free analog-to-digital converter (ADC). The new structure solves the problem that the number of comparators in the fine ADC is increased as the number of bits is increased. The power dissipation of the comparator is explored and an innovative bisection MSB comparator is designed to further reduce power consumption and chip area of the new ADC. According to the simulation results, the new ADC can achieve 10-bit resolution and 2 MHz input bandwidth at a sampling rate of 5 MHz using 5 V 0.8 um CMOS process. The active die size is 1.4/spl times/2.2 mm/sup 2/ and the power dissipation is 175 mW at 5 V.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128682746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Designing PCI bus interfaces with programmable logic 用可编程逻辑设计PCI总线接口
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580740
B. Fawcett
{"title":"Designing PCI bus interfaces with programmable logic","authors":"B. Fawcett","doi":"10.1109/ASIC.1995.580740","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580740","url":null,"abstract":"PCI-compliant high-density programmable logic devices can be used to create flexible PCI bus interfaces while avoiding the costs and risks of custom IC development. However, careful design is required to meet the performance and signaling requirements of the PCI specification. This paper focuses on the attributes needed in programmable logic devices to facilitate interface design, and suggests appropriate design techniques.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126230638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low-cost realization of multiple-input exclusive-OR gates 多输入异或门的低成本实现
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580737
Kun-Jin Lin, Cheng-Wen Wu
{"title":"A low-cost realization of multiple-input exclusive-OR gates","authors":"Kun-Jin Lin, Cheng-Wen Wu","doi":"10.1109/ASIC.1995.580737","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580737","url":null,"abstract":"Several efficient CMOS two-input exclusive-OR (XOR) logic structures have been reported in the past. Based on these XOR gates, we propose two multiple-input XOR circuit configurations, which are smaller, faster, and run at a lower power level than conventional structures formed by directly connecting two-input XOR gates. For exclusive-OR sum-of-products circuits, four transistors can be saved for each product term.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125238253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Fast coupled noise calculation for crosstalk avoidance in MCM autorouting MCM自动路由中串扰避免的快速耦合噪声计算
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580671
T. Hameenanttila, J. Carothers
{"title":"Fast coupled noise calculation for crosstalk avoidance in MCM autorouting","authors":"T. Hameenanttila, J. Carothers","doi":"10.1109/ASIC.1995.580671","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580671","url":null,"abstract":"A fast method of crosstalk noise avoidance for correct-by-design MCM routing is discussed. During substrate routing, coupled noise in nets is calculated and noise amplitudes exceeding coupled noise budgets are corrected as part of the routing process. This represents an improvement over the heuristic noise reduction methods employed by some MCM routers and geometrical wiring rules generated by detailed simulation used by others. Lookup tables of coupling data are used in conjunction with closed-form equations in order to obtain noise estimates quickly. The method is applicable to a wide variety of MCM technologies without alteration, since the noise estimation is based only on interconnect geometry and the dielectric constant of the medium. The correctness of the noise estimation has been verified using a transmission line simulator and the effect of the procedure on the routing density achieved by an MCM autorouter has been investigated.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127220905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A CMOS, self calibrating, 100 MHz RC-oscillator for ASIC applications 一个CMOS，自校准，100兆赫rc振荡器用于ASIC应用
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580732
T. O'Shaughnessy
{"title":"A CMOS, self calibrating, 100 MHz RC-oscillator for ASIC applications","authors":"T. O'Shaughnessy","doi":"10.1109/ASIC.1995.580732","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580732","url":null,"abstract":"The design of a high performance cell based CMOS rc-oscillator for ASIC applications is presented. The oscillator operates over a wide voltage range that includes 3.0 volt operation. The circuit features low operating current and low temperature sensitivity. The frequency accuracy is dominated only by the tolerances of the R and C elements. Circuit theory, simulations and measured performance are presented.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117057997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Near-sensor image processing, a VLSI realization 近传感器图像处理，一个VLSI实现
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580687
J. Eklund, C. Svensson, A. Astrom
{"title":"Near-sensor image processing, a VLSI realization","authors":"J. Eklund, C. Svensson, A. Astrom","doi":"10.1109/ASIC.1995.580687","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580687","url":null,"abstract":"We present a single chip circuit solution to a concept called Near-Sensor Image Processing (NISP), which includes image sensing, image processing and feature extraction. We give solutions to the three main implementation problems. A small photodiode read-out unit, which is locally compensated for process variations, a low power processor element and an instruction line driver, suitable for massively parallel processors are described. A 16/spl times/16 elements prototype has been built. However most of the results come from simulations of an improved 128/spl times/128 matrix.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114485546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
NetConf: a single chip PCM conference circuit with automatic gain control, attenuation, noise suppression, soft reset and multiple frame synchronization timing NetConf:单片PCM会议电路，具有自动增益控制、衰减、噪声抑制、软复位和多帧同步定时功能
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580712
G. Kuru
{"title":"NetConf: a single chip PCM conference circuit with automatic gain control, attenuation, noise suppression, soft reset and multiple frame synchronization timing","authors":"G. Kuru","doi":"10.1109/ASIC.1995.580712","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580712","url":null,"abstract":"This paper presents a unique 2-stage pipeline PCM conference architecture, called NetConf, specially designed and realized as a single chip VLSI for processing PCM channels in order to provide conference in digital switching systems. The NetConf conference circuit overcomes the manual handling of overflow problem, that exist in the current architectures, with a unique 2-stage pipelined architecture and a new AGC algorithm. The circuit can also provide regular connection and capable of doing 3 Level attenuation, 4 level noise suppression on all or any selected channel. The circuit can be soft reset and accept different frame synchronization timings. The conference circuit realized by European Silicon Structures' 0.7 micron CMOS technology and packaged in a 24 pin plastic DIL package. The die is 12 mm/sup 2/ and consists of 12,000 gates including two four-ports static RAMs. This newly proposed 2-stage pipeline conference architecture provides better overflow and noise performance over existing architectures.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129358226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transient waveform response of distributed loaded RC thin film structure for voltage step function using Laplace transformation 基于拉普拉斯变换的分布加载RC薄膜结构电压阶跃函数的瞬态波形响应
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580703
K. El-Shennawy, G. P. Fiani, M. Tayel
{"title":"Transient waveform response of distributed loaded RC thin film structure for voltage step function using Laplace transformation","authors":"K. El-Shennawy, G. P. Fiani, M. Tayel","doi":"10.1109/ASIC.1995.580703","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580703","url":null,"abstract":"This paper presents closed form solution of uniformly distributed resistively loaded RC thin film structure for voltage step input function, using bisection technique, Laplace transformation, Heaviside theorem and contour integration algorithms. Two different methods are introduced: Maclorin method and iterative method. The voltage and current transient responses are plotted for different normalized load and time parameters. Verification of the results has been done and lies between the open and shorted solutions.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127901018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A simulation tool for dynamically reconfigurable field programmable gate arrays 动态可重构现场可编程门阵列的仿真工具
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580707
P. Lysaght, J. Stockwood
{"title":"A simulation tool for dynamically reconfigurable field programmable gate arrays","authors":"P. Lysaght, J. Stockwood","doi":"10.1109/ASIC.1995.580707","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580707","url":null,"abstract":"The emergence of static memory-based FPGAs that are capable of being dynamically reconfigured, i.e. partially reconfigured while active, has resulted in research into new methods of digital systems synthesis. At present, however, there are virtually no CAD tools to support the design of digital systems using dynamic reconfiguration. This paper reports on an investigation of new simulation tools and the development of a new simulation technique for dynamically reconfigurable systems.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132729517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 107
On the complexity of bridging fault simulation techniques for CMOS integrated circuits CMOS集成电路桥接故障仿真技术的复杂性
Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-09-18 DOI: 10.1109/ASIC.1995.580705
C. A. Ryan
{"title":"On the complexity of bridging fault simulation techniques for CMOS integrated circuits","authors":"C. A. Ryan","doi":"10.1109/ASIC.1995.580705","DOIUrl":"https://doi.org/10.1109/ASIC.1995.580705","url":null,"abstract":"Accepted integrated circuit verification techniques involve stuck-at fault simulation. However, it has been shown that the majority of actual physical faults in the faulty integrated circuit are bridging faults. For this reason, the interest in bridging fault simulation techniques has increased. One characteristic with bridging faults is that the bridging fault may have electrical as well as logical behavior. This characteristic makes detection of bridging faults more difficult and this characteristic increases the complexity of bridging fault simulation. The three techniques most widely used for bridging fault simulation are current testing, stuck-at testing and delay testing. This paper compares the complexity and robustness of the three techniques and new developments in the three techniques. Results show the current testing technique to be the most robust and have the lowest complexity which approaches that of stuck-at fault simulation complexity.","PeriodicalId":307095,"journal":{"name":"Proceedings of Eighth International Application Specific Integrated Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131969680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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