Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on最新文献

筛选
英文 中文
Arsenic dimer implants for shallow extension in 0.13μm logic devices 用于0.13 μ m逻辑器件浅层扩展的砷二聚体植入物
B. Chang, J. Chang, A. Agarwal, M. Ameen, R. Reece, H. Chen, D. Chien, C. Tsai, M. Tsai, C. Weng, D. Wu, C. Yang
{"title":"Arsenic dimer implants for shallow extension in 0.13μm logic devices","authors":"B. Chang, J. Chang, A. Agarwal, M. Ameen, R. Reece, H. Chen, D. Chien, C. Tsai, M. Tsai, C. Weng, D. Wu, C. Yang","doi":"10.1109/IIT.2002.1257951","DOIUrl":"https://doi.org/10.1109/IIT.2002.1257951","url":null,"abstract":"Arsenic dimer, As2+, implants have been used for the formation of ultra-shallow source drain extensions for NMOS transistors in a 0.13 μm, 1.5 V CMOS logic process. A comparison of all electrical parameters including drive currents, sheet resistance, junction breakdown voltages and gate to drain capacitance indicate equivalent process performance for monomer and dimer implants. Arsenic dimer and monomer implants were also compared using bare silicon control wafers in both drift and decel mode. The dimer implants were found to be energy contamination free. The use of dimer implants resulted in machine throughput improvement of 4× without any adverse impact on the implanter performance in terms of ion source lifetime, particles, or implant uniformity.","PeriodicalId":305062,"journal":{"name":"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114749044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An enhanced 100nm CMOS logic technology with germanium preamorphized PMOS 基于锗预非晶化PMOS的100nm CMOS逻辑增强技术
S.T.H. Chan, F. Benistant, A. Al-Bayati
{"title":"An enhanced 100nm CMOS logic technology with germanium preamorphized PMOS","authors":"S.T.H. Chan, F. Benistant, A. Al-Bayati","doi":"10.1109/IIT.2002.1257940","DOIUrl":"https://doi.org/10.1109/IIT.2002.1257940","url":null,"abstract":"80nm physical gate length CMOS technology using germanium preamorphization implantation (Ge PAI) has been developed. With optimum Ge PAI conditions, PMOS device performance enhancement can be achieved through improved dopant activation at S/D extension region while short channel effects are also reduced. It is also shown, for the first time, that Ge PAI at S/D junction can also achieve performance enhancement depending on device architecture.","PeriodicalId":305062,"journal":{"name":"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133399321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Gas cluster ion beam processing equipment 气簇离子束加工设备
J. Bachand, A. Freytsis, E. Harrington, M. Gwinn, N. Hofmeester, J. Hautala, M. Mack, K. Regan
{"title":"Gas cluster ion beam processing equipment","authors":"J. Bachand, A. Freytsis, E. Harrington, M. Gwinn, N. Hofmeester, J. Hautala, M. Mack, K. Regan","doi":"10.1109/IIT.2002.1258094","DOIUrl":"https://doi.org/10.1109/IIT.2002.1258094","url":null,"abstract":"Gas cluster ion beams (GCIB) are finding many applications for surface smoothing and etching of a variety of materials including semiconductors. Epion has developed commercial processing equipment, which makes possible practical application of GCIB beams for production processes. This equipment includes automatic recipe setup and tracking. Process uniformity and repeatability has been demonstrated to be better than 1%. Charge control keeps substrate charging to less than ±6 V. Throughputs as high as 10 W/hr are achievable with 200 mm wafers.","PeriodicalId":305062,"journal":{"name":"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129347105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
In-line measurement of Xj on 300 mm wafers 在300mm晶圆上在线测量Xj
S. Corcoran, P. Gillespie, M. Segovia, P. Borden
{"title":"In-line measurement of Xj on 300 mm wafers","authors":"S. Corcoran, P. Gillespie, M. Segovia, P. Borden","doi":"10.1109/IIT.2002.1257965","DOIUrl":"https://doi.org/10.1109/IIT.2002.1257965","url":null,"abstract":"Process control issues are insufficiently addressed by current metrology for USJ formation on 300 mm wafers at advanced technology nodes. The Carrier Illumination™ technique, an in-line optical approach, is examined for use in process control (SPC) and implant/anneal root-cause isolation (characterization).","PeriodicalId":305062,"journal":{"name":"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122275187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Charging effects on medium current implanter on CMOS and mixed signal IC's CMOS和混合信号集成电路中电流注入器的充电效应
T. Gandy, V. Sargūnas, A. Singh, S. Taduri, P. Thiefain, M. Ameen, R. Rathmell
{"title":"Charging effects on medium current implanter on CMOS and mixed signal IC's","authors":"T. Gandy, V. Sargūnas, A. Singh, S. Taduri, P. Thiefain, M. Ameen, R. Rathmell","doi":"10.1109/IIT.2002.1257998","DOIUrl":"https://doi.org/10.1109/IIT.2002.1257998","url":null,"abstract":"Stringent process performance requirements for advanced devices have led to hardware specifically optimized for low metal contamination and particle contribution during implants and wafer handling. Electrostatic chucks (ESC) serve this purpose particularly well in single wafer processing machines in that the area of the wafer holder exposed to the beam can be nearly completely eliminated. One potential disadvantage of this is that secondary electrons are no longer generated in the wafer vicinity to neutralize the beam. Wafer charging was observed for certain implant levels for CMOS and mixed signal integrated circuits, implanted on an Axcelis 8200/8250 medium current implanter with the Electrostatic Chuck using no electron shower for beam neutralization. The charging effects were manifested as blowouts/arcing defects on the silicon surface, as verified by in-line defectivity metrology. Depressed yield was also observed for the wafers impacted by the charging problem even in the case with no visible in-line defectivity. The charging intensity and resulting extent of damage was found to vary with beam current. Addition of secondary electron shower module to provide charge control is shown to eliminate the problem. Wafer charging in response to various settings of electron shower primary current is discussed by review of in-line defectivity/silicon damage measurements and end of the line yield data. Equipment and process optimizations to improve system performance and stability are summarized.","PeriodicalId":305062,"journal":{"name":"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122349828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimization of high tilt pocket implant process for improving deep sub-micro PMOS device sensitivity 提高深亚微PMOS器件灵敏度的高倾角口袋植入工艺优化
Kun-Yang Yeh, M. Chiang, C. Tsai, Y. L. Wang, J. K. Wang
{"title":"Optimization of high tilt pocket implant process for improving deep sub-micro PMOS device sensitivity","authors":"Kun-Yang Yeh, M. Chiang, C. Tsai, Y. L. Wang, J. K. Wang","doi":"10.1109/IIT.2002.1257926","DOIUrl":"https://doi.org/10.1109/IIT.2002.1257926","url":null,"abstract":"High tilt pocket implants are evaluated for various conditions of tilt and twist combination. The effects of tilt angle on both sheet resistance (Rs) and 0.13 μm PMOS device characteristics are investigated. By variation of tilt angle it is shown that. both lateral dopant profile of pocket implant and substrate channeling effect will dominate the PMOS device sensitivity. A simple solution to good device stability by employing the channeling effect is demonstrated. With the assist of crystal channel at specific tilt and twist angle, the PMOS drive current sensitivity to tilt angle will be greatly reduced by 67% to 0.03 mA/degree and below.","PeriodicalId":305062,"journal":{"name":"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124698518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Photoresist wafer processing with the SWIFT ion implanter SWIFT离子注入器的光刻胶晶圆加工
K. Mast, R. Low, D. Knowles, M. Junker
{"title":"Photoresist wafer processing with the SWIFT ion implanter","authors":"K. Mast, R. Low, D. Knowles, M. Junker","doi":"10.1109/IIT.2002.1257999","DOIUrl":"https://doi.org/10.1109/IIT.2002.1257999","url":null,"abstract":"Photoresist (PR) outgassing during implantation can be significant for high current, high energy implants, and if ignored, can result in dose variations. The SWIFT ion implanter uses an intelligent software algorithm in conjunction with fast beam sampling to allow the system to reliably compensate for photoresist outgassing, allowing excellent wafer-to-wafer dose repeatability. In addition, the beam charge recovery tolerance has been made configurable, to allow easy optimization of system throughput versus dose control. In this paper, performance data is presented for photoresist wafers implanted using the intelligent software algorithm compared to bare wafers implanted under identical conditions.","PeriodicalId":305062,"journal":{"name":"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124840308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of tilt angle variation on device performance 倾斜角度变化对设备性能的影响
D. Lenoble, F. Wacquant, E. Josse, F. Arnaud
{"title":"Impact of tilt angle variation on device performance","authors":"D. Lenoble, F. Wacquant, E. Josse, F. Arnaud","doi":"10.1109/IIT.2002.1257934","DOIUrl":"https://doi.org/10.1109/IIT.2002.1257934","url":null,"abstract":"The control of tilt/twist angles during ion implantation process is becoming one the most challenging issue for future CMOS technologies. The continuous shrink of CMOS device dimensions imposes an accurate dopant placement within the transistor architecture. Moreover, improvement in the packing density increases the shadowing impact of resist patterns, leading to the use of quasi-vertical implants. In this paper, we propose to experimentally determine the sensitivity of standard electrical parameters of advanced technologies, sub-0.13-μm, to tilt angle variations that may occur within a wafer, within a lot, or lot to lot. Critical implants such as the high tilt implants (pockets) are studied for pMOS and nMOS transistors. Nominal results, obtained with the nominal tilt angle, are compared to the electrical results (threshold voltage, Ion/Ioff, Short Channel Effects...) obtained for a modified tilt angle (+/-3°). Curves of sensitivity are then extracted. As a conclusion, specifications for the angle accuracy are proposed in order to insure a perfect matching of the device performance whatever the tilt angle discrepancies are.","PeriodicalId":305062,"journal":{"name":"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127953325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Selective silicon processing for advanced ultra shallow junction engineering 先进超浅结工程的选择性硅加工
L. Scudder, A. Al-Bayati
{"title":"Selective silicon processing for advanced ultra shallow junction engineering","authors":"L. Scudder, A. Al-Bayati","doi":"10.1109/IIT.2002.1257946","DOIUrl":"https://doi.org/10.1109/IIT.2002.1257946","url":null,"abstract":"As the semiconductor design rules continue to shrink, new device processing issues continue to be identified. One issue facing ultra shallow junction CMOS structures is the contact resistance and silicon consumption for silicide in the active source/drain regions of the device. A sacrificial selective silicon layer for elevating the source and drain (S/D) is considered to be a potential solution to metalization issues for 0.1μm devices and beyond. A production worthy selective silicon process has several key control parameters. This paper presents information on the critical processing parameters such as interface contamination control, and the selective silicon process window. Growth results for a single wafer selective elevated S/D process are also presented.","PeriodicalId":305062,"journal":{"name":"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126205747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Advantages of single and mixed species chaining for high productivity in high and mid-energy implantation 单种和混合种连锁在高中能植入中高产率的优势
S. Nitodas, M. Ameen, L. Rubin
{"title":"Advantages of single and mixed species chaining for high productivity in high and mid-energy implantation","authors":"S. Nitodas, M. Ameen, L. Rubin","doi":"10.1109/IIT.2002.1257966","DOIUrl":"https://doi.org/10.1109/IIT.2002.1257966","url":null,"abstract":"Chaining implant steps improve device performance and yield, enhance throughput, and reduce manufacturing time, cost and risk. A typical implant chain consists of two to four steps of varying energy, dose and Implant angle, and may also include multiple species. High-energy (HE) well implants, including threshold voltage (Vt) adjusts, are Ideal candidates for chaining due to their location in the process flow, similarity in mask sets, and beam current requirements. In the present study, we prove feasibility of same species\"\" and \"\"mixed species\"\" chains with high throughput in multi-wafer ion implanters. Throughput models have been generated to examine how mixed species chains improve machine productivity. Optimization of chains is achieved through characterization of the hardware and optimization of the software to allow for flexibility In setting up and running chains. Measurements of energetic and surface contamination in the mixed species chains demonstrate the implanter's capability of running chains without any contamination problems. Results on tune/transition times between chain recipes are presented, and subsequent throughput enhancements are discussed.","PeriodicalId":305062,"journal":{"name":"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124020291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信