An enhanced 100nm CMOS logic technology with germanium preamorphized PMOS

Abstract

80nm physical gate length CMOS technology using germanium preamorphization implantation (Ge PAI) has been developed. With optimum Ge PAI conditions, PMOS device performance enhancement can be achieved through improved dopant activation at S/D extension region while short channel effects are also reduced. It is also shown, for the first time, that Ge PAI at S/D junction can also achieve performance enhancement depending on device architecture.