Selective silicon processing for advanced ultra shallow junction engineering

Abstract

As the semiconductor design rules continue to shrink, new device processing issues continue to be identified. One issue facing ultra shallow junction CMOS structures is the contact resistance and silicon consumption for silicide in the active source/drain regions of the device. A sacrificial selective silicon layer for elevating the source and drain (S/D) is considered to be a potential solution to metalization issues for 0.1μm devices and beyond. A production worthy selective silicon process has several key control parameters. This paper presents information on the critical processing parameters such as interface contamination control, and the selective silicon process window. Growth results for a single wafer selective elevated S/D process are also presented.