基于锗预非晶化PMOS的100nm CMOS逻辑增强技术

Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on Pub Date : 1900-01-01 DOI:10.1109/IIT.2002.1257940

S.T.H. Chan, F. Benistant, A. Al-Bayati

{"title":"基于锗预非晶化PMOS的100nm CMOS逻辑增强技术","authors":"S.T.H. Chan, F. Benistant, A. Al-Bayati","doi":"10.1109/IIT.2002.1257940","DOIUrl":null,"url":null,"abstract":"80nm physical gate length CMOS technology using germanium preamorphization implantation (Ge PAI) has been developed. With optimum Ge PAI conditions, PMOS device performance enhancement can be achieved through improved dopant activation at S/D extension region while short channel effects are also reduced. It is also shown, for the first time, that Ge PAI at S/D junction can also achieve performance enhancement depending on device architecture.","PeriodicalId":305062,"journal":{"name":"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on","volume":"213 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An enhanced 100nm CMOS logic technology with germanium preamorphized PMOS\",\"authors\":\"S.T.H. Chan, F. Benistant, A. Al-Bayati\",\"doi\":\"10.1109/IIT.2002.1257940\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"80nm physical gate length CMOS technology using germanium preamorphization implantation (Ge PAI) has been developed. With optimum Ge PAI conditions, PMOS device performance enhancement can be achieved through improved dopant activation at S/D extension region while short channel effects are also reduced. It is also shown, for the first time, that Ge PAI at S/D junction can also achieve performance enhancement depending on device architecture.\",\"PeriodicalId\":305062,\"journal\":{\"name\":\"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on\",\"volume\":\"213 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIT.2002.1257940\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIT.2002.1257940","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

提出了采用锗预非晶化注入(Ge PAI)的80nm物理栅长CMOS技术。在最佳的Ge PAI条件下，PMOS器件的性能可以通过改善S/D扩展区域的掺杂激活来提高，同时也可以减少短通道效应。研究还首次表明，在S/D结处的Ge PAI也可以根据器件架构实现性能增强。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

An enhanced 100nm CMOS logic technology with germanium preamorphized PMOS

80nm physical gate length CMOS technology using germanium preamorphization implantation (Ge PAI) has been developed. With optimum Ge PAI conditions, PMOS device performance enhancement can be achieved through improved dopant activation at S/D extension region while short channel effects are also reduced. It is also shown, for the first time, that Ge PAI at S/D junction can also achieve performance enhancement depending on device architecture.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on

自引率

0.00%

发文量