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2009 IEEE International Interconnect Technology Conference最新文献

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Performance Comparison between capacitively driven low swing and conventional interconnects for CU and carbon nanotube wire technologies 电容驱动低摆幅与传统铜和碳纳米管线互连技术的性能比较
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090330
Kyung-Hoae Koo, P. Kapur, Jeongha Park, Hyunjong Noh, S. Wong, K. Saraswat
{"title":"Performance Comparison between capacitively driven low swing and conventional interconnects for CU and carbon nanotube wire technologies","authors":"Kyung-Hoae Koo, P. Kapur, Jeongha Park, Hyunjong Noh, S. Wong, K. Saraswat","doi":"10.1109/IITC.2009.5090330","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090330","url":null,"abstract":"The on-chip interconnect bottleneck with conventional Cu/low-k and delay optimized repeater scheme presents a compelling reason to explore novel interconnect circuit architectures. The capacitively driven low-swing interconnect (CDLSI) has the potential to affect a significant energy saving and latency reduction. The purpose of this work is two fold: Firstly, to develop an accurate analytical, optimized model for CDLSI wire scheme; Secondly, to quantify and compare the delay and energy expenditure for not only different interconnect circuit schemes, but also various future technologies such as Cu, carbon nanotube and optics. We find that CDLSI circuit scheme outperforms the conventional interconnects in latency and energy per bit for lower bandwidth requirement, while these advantages degrade for higher bandwidth requirements.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"2000 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123753992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Integration and reliability of CVD Ru cap for Cu/Low-k development 用于Cu/Low-k开发的CVD Ru帽的集成和可靠性
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090402
C. Yang, Daniel C. Edelstein, Kaushik Chanda, Ping-Chuan Wang, Chenming Hu, E. Liniger, Stephan A. Cohen, James R. Lloyd, Baozhen Li, F. Mcfeely, R. Wisnieff, T. Ishizaka, F. M. Cerio, K. Suzuki, Jonathan Rullan, A. Selsley, M. Jomen
{"title":"Integration and reliability of CVD Ru cap for Cu/Low-k development","authors":"C. Yang, Daniel C. Edelstein, Kaushik Chanda, Ping-Chuan Wang, Chenming Hu, E. Liniger, Stephan A. Cohen, James R. Lloyd, Baozhen Li, F. Mcfeely, R. Wisnieff, T. Ishizaka, F. M. Cerio, K. Suzuki, Jonathan Rullan, A. Selsley, M. Jomen","doi":"10.1109/IITC.2009.5090402","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090402","url":null,"abstract":"Selective CVD Ru cap deposition process has been developed for BEOL Cu/Low-k integration. Selectivity of CVD Ru deposition between Cu and dielectrics is investigated. Electrical performance, electromigration (EM) lifetime, voltage ramp (I–V), and time -dependent-dielectric-breakdown (TDDB) are also characterized for Cu interconnects capped with CVD Ru. This selective CVD Ru cap process is a good candidate for 22nm and beyond technology nodes.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126131719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Synchrotron measurement of the effect of dielectric porosity and air gaps on the stress in advanced Cu/Low-k interconnects 超前Cu/Low-k互连中介电孔隙率和气隙对应力影响的同步加速器测量
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090343
C. Wilson, C. Zhao, L. Zhao, Z. Tokei, K. Croes, M. Pantouvaki, G. Beyer, A. Horsfall, A. O'Neill
{"title":"Synchrotron measurement of the effect of dielectric porosity and air gaps on the stress in advanced Cu/Low-k interconnects","authors":"C. Wilson, C. Zhao, L. Zhao, Z. Tokei, K. Croes, M. Pantouvaki, G. Beyer, A. Horsfall, A. O'Neill","doi":"10.1109/IITC.2009.5090343","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090343","url":null,"abstract":"The stress of Cu interconnects embedded in advanced ultra-low-k (ULK) dielectrics was studied for different porosities. Interconnects formed a high porosity material result in a lower stress due to relaxation in the plane. This effect is less significant for narrow lines, where in-plane relaxation is reduced by the dense narrow spacing. The stress in isolated lines was found to be independent of dielectric porosity. We also studied air gap structures, showing the lowest stress. This work will be useful when interpreting reliability failure mechanisms and calibrating finite element models to predict stress in devices of future technology nodes.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114853669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Plasma altered layer model for plasma damage characterization of porous OSG films 多孔OSG薄膜等离子体损伤表征的等离子体改变层模型
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090345
H. Shi, H. Huang, J. Bao, J. Im, P. Ho, Y. Zhou, J. Pender, M. Armacost, D. Kyser
{"title":"Plasma altered layer model for plasma damage characterization of porous OSG films","authors":"H. Shi, H. Huang, J. Bao, J. Im, P. Ho, Y. Zhou, J. Pender, M. Armacost, D. Kyser","doi":"10.1109/IITC.2009.5090345","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090345","url":null,"abstract":"A plasma altered layer model was developed to characterize plasma damage in porous OSG (organosilicate glass) low-k dielectrics by taking into account the kinetics of radical diffusion, reaction, and recombination. A gap structure was designed to study plasma damage and validate the model. It consisted of two parallel rectangular Si spacers and a top optical mask to control the energy and intensity of ion, photon, and radical in the plasma. CO2 and O2 plasma-induced damages were found to depend on the radical concentration, the energy and intensity of VUV photons, the ion energy, and the substrate temperature. Overall, the results obtained from plasma damage studies were consistent with the prediction of the model. The application of the model was demonstrated in a study of He plasma pretreatment and damage formation in OSG films with varying carbon concentrations. Both treatments were found to be effective in improving the material resistance to plasma damage.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127805211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Impact of chip package interaction on Cu/Ultra low-k interconnect delamination in Flip Chip Package with large die 芯片封装相互作用对大芯片倒装封装中Cu/超低k互连分层的影响
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090392
C. Uchibori, Michael Lee
{"title":"Impact of chip package interaction on Cu/Ultra low-k interconnect delamination in Flip Chip Package with large die","authors":"C. Uchibori, Michael Lee","doi":"10.1109/IITC.2009.5090392","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090392","url":null,"abstract":"Die size effects on Chip Package Interaction for Cu/Ultra low-k interconnect in Flip Chip Package were investigated using mechanical and thermal analysis. The analytical and the theoretical study suggested that the die size effects were not caused only by the mismatch in CTE between die and substrate. By considering the number of bonding solder and its mechanical property during the cooling process, the die size dependency of CPI was successfully demonstrated.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"45 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132696370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On chip monitoring of via degradation 芯片上监测通孔劣化
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090364
Fahad Ahmed, L. Milor
{"title":"On chip monitoring of via degradation","authors":"Fahad Ahmed, L. Milor","doi":"10.1109/IITC.2009.5090364","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090364","url":null,"abstract":"The delays of paths in a chip can be monitored to detect via voiding. This work relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65nm technology. The sensitivity of the trigger point as a function of the failure distribution parameters and the path length has been investigated. A circuit has been designed to detect the onset of chip failure due to via voiding.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"1994 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131147048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel high coplanarity lead free copper pillar bump fabrication process 一种新型的高共面性无铅铜柱凹凸加工工艺
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090377
Hou-Jun Hsu, Jung-Tang Huang, Kuo-Yu Lee, R. Wu, T. Tsai
{"title":"A novel high coplanarity lead free copper pillar bump fabrication process","authors":"Hou-Jun Hsu, Jung-Tang Huang, Kuo-Yu Lee, R. Wu, T. Tsai","doi":"10.1109/IITC.2009.5090377","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090377","url":null,"abstract":"In this paper, we report a novel plating-friendly polishing mechanism for fabrication of high coplanarity and high density lead-free copper pillar bumps for advanced packaging applications. The final experimental results showed that the UIW (Uniformity in Wafer) could be sharply decreased from 6.37% after plating to 1.7% after polishing and even to 1.7% after reflow throughout the entire 4 inch wafer.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127057755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Co-design of reliable signal and power interconnects in 3D stacked ICs 三维堆叠集成电路中可靠信号与电源互连的协同设计
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090339
Young-Joon Lee, Michael B. Healy, S. Lim
{"title":"Co-design of reliable signal and power interconnects in 3D stacked ICs","authors":"Young-Joon Lee, Michael B. Healy, S. Lim","doi":"10.1109/IITC.2009.5090339","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090339","url":null,"abstract":"With the rapid advance of die stacking and through-silicon-via fabrication technologies, the era of 3D ICs is near. Yet, the knowledge base of 3D IC design techniques is still not matured enough. In this paper, we investigate the design issues raised during the system-level integration of signal and power interconnects in 3D ICs. Routing congestion and power noise are analyzed, and various factors that affect performance and reliability metrics are identified.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114633497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
SMAFTI packaging technology for new interconnect hierarchy SMAFTI封装技术用于新的互连层次结构
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090393
Y. Kurita, N. Motohashi, S. Matsui, K. Soejima, S. Amakawa, K. Masu, M. Kawano
{"title":"SMAFTI packaging technology for new interconnect hierarchy","authors":"Y. Kurita, N. Motohashi, S. Matsui, K. Soejima, S. Amakawa, K. Masu, M. Kawano","doi":"10.1109/IITC.2009.5090393","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090393","url":null,"abstract":"We have developed a 3-D packaging technology called SMAFTI (SMArt chip connection with FeedThrough Interposer), which enables the implementation of a new memory/logic-interconnect hierarchy. Through experiments, we were able to confirm practical performance of this technology. We implemented a new die bonding process and the multilayer interconnect technology to form over a thousand parallel interconnects between memory and logic dies. Implementation of the new process was achieved with high productivity and low process costs. We characterized the interlaminar horizontal wiring by S-parameter measurement up to 40 GHz and confirmed its potential for high-speed signal transmission at over 10 Gb/s.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132959476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Optimized integrated copper gap-fill approaches for 2x flash devices 优化集成铜隙填充方法的2x闪存器件
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090334
P. Ma, Qian Luo, A. Sundarrajan, J. Lu, J. Aubuchon, J. Tseng, Niranjan Kumar, M. Okazaki, Yuchun Wang, You Wang, Yufei Chen, M. Naik, I. Emesh, M. Narasimhan
{"title":"Optimized integrated copper gap-fill approaches for 2x flash devices","authors":"P. Ma, Qian Luo, A. Sundarrajan, J. Lu, J. Aubuchon, J. Tseng, Niranjan Kumar, M. Okazaki, Yuchun Wang, You Wang, Yufei Chen, M. Naik, I. Emesh, M. Narasimhan","doi":"10.1109/IITC.2009.5090334","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090334","url":null,"abstract":"Physical vapor deposited (PVD) Cu seed layers have been successfully implemented for Cu gap-fill in feature sizes for the 2x nm flash devices. By tuning the incident angle of the incoming flux of Cu ions as well as utilizing the resputtering parameter, the overhang, sidewall coverage and asymmetry can be well controlled to enable complete fill by subsequent electrochemical deposition (ECD). Chemical vapor deposition (CVD) Cobalt (Co) films were also investigated as an enhancement layer for Cu gap-fill. It was observed that the insertion of a 1.5nm-thick CVD Co layer, deposited between a PVD Ta barrier and a Cu seed layer could effectively enhance gap-fill in the small geometry trench/via structures. The CVD Co enhancement layer could also significantly improve the electromigration (EM) resistance of the Cu interconnects. The Chemical Mechanical Polish (CMP) process was also developed to provide an integrated solution.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134347177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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