芯片上监测通孔劣化

2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI:10.1109/IITC.2009.5090364

Fahad Ahmed, L. Milor

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引用次数: 0

摘要

芯片中路径的延迟可以通过空化来监测和检测。这项工作将单个通孔的故障概率与使用65nm技术的数据的系统监视器延迟的增加联系起来。研究了触发点的灵敏度随故障分布参数和路径长度的变化规律。设计了一种电路，用于检测由于漏孔引起的芯片故障。

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On chip monitoring of via degradation

The delays of paths in a chip can be monitored to detect via voiding. This work relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65nm technology. The sensitivity of the trigger point as a function of the failure distribution parameters and the path length has been investigated. A circuit has been designed to detect the onset of chip failure due to via voiding.

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2009 IEEE International Interconnect Technology Conference

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