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Constant field stressing of via-to-line spacing for accurate projection of intrinsic TDDB lifetime 为准确预测TDDB固有寿命，通过孔到线间距的恒定场应力
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090383
T. Kamoshima, K. Makabe, M. Amishiro, T. Furusawa, Y. Takata, M. Ogasawara
{"title":"Constant field stressing of via-to-line spacing for accurate projection of intrinsic TDDB lifetime","authors":"T. Kamoshima, K. Makabe, M. Amishiro, T. Furusawa, Y. Takata, M. Ogasawara","doi":"10.1109/IITC.2009.5090383","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090383","url":null,"abstract":"We proposed solutions for determining the accurate projection of the TDDB lifetime of via-to-line spacing; that is, using a single-via test structure and constant field stress. This method eliminates the lifetime variations due to the spacing variations more effectively than conventional methods, for example, area scaling. The projected lifetime under the given use conditions increased at least about two-orders of magnitude by using this method, showing that constant field stress can be used to effectively project intrinsic TDDB lifetimes.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130860576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Novel dielectric deposition technology for advanced interconnect with air gap 先进气隙互连介质沉积新技术
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090333
J. Faguet, Eric P. Lee, Junjun Liu, J. Brcka, O. Akiyama
{"title":"Novel dielectric deposition technology for advanced interconnect with air gap","authors":"J. Faguet, Eric P. Lee, Junjun Liu, J. Brcka, O. Akiyama","doi":"10.1109/IITC.2009.5090333","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090333","url":null,"abstract":"A Filament-Assisted Chemical Vapor Deposition (FACVD) concept for back-end-of-line (BEOL) applications is presented. Key capabilities of this technology include low-temperature plasma-free film deposition with straightforward scalability and extendibility. Deposition mechanism and film properties are compared with conventional plasma-enhanced CVD (PECVD). FACVD deposition of a decomposable polymer and a porous low-k organosilicate cap is demonstrated to build air gap structures. Other FACVD applications are also discussed.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121598261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Key Process steps for high reliable SiOCH low-k dielectrics for the sub 45nm technology nodes 用于45纳米以下技术节点的高可靠SiOCH低k电介质的关键工艺步骤
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090359
M. Vilmay, D. Roy, C. Besset, D. Galpin, C. Monget, P. Vannier, Y. Le Friec, G. Imbert, M. Mellier, S. Petitdidier, O. Robin, J. Guillan, S. Chhun, L. Arnaud, F. Volpi, J. Chaix
{"title":"Key Process steps for high reliable SiOCH low-k dielectrics for the sub 45nm technology nodes","authors":"M. Vilmay, D. Roy, C. Besset, D. Galpin, C. Monget, P. Vannier, Y. Le Friec, G. Imbert, M. Mellier, S. Petitdidier, O. Robin, J. Guillan, S. Chhun, L. Arnaud, F. Volpi, J. Chaix","doi":"10.1109/IITC.2009.5090359","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090359","url":null,"abstract":"The introduction of SiOCH low-k dielectrics in copper interconnects associated to the reduction of the critical dimensions in advanced technology nodes is becoming a major reliability concern. The interconnect realization requires a consequent number of critical process steps [1]. Since porous low-k dielectrics are used as Inter-Metal Dielectric (IMD) each process step can be a source of degradation for the dielectric. This paper describes critical process steps influencing the low-k reliability. All the processes affecting the dielectric's interfaces are also evidenced to degrade the low-k interconnect robustness. Some process examples as the direct chemical and mechanical polishing (CMP), the slurry chemistry and the TaN/Ta barrier etching are details in this paper. Moreover, some process options are given to strongly improve low-k dielectric reliability without degradation of its electrical performances.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115438647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Demonstration of TFHM scalability to 32 nm node BEOL interconnect and extendibility to ELK k ≤ 2.3 dielectric material 演示TFHM可扩展到32 nm节点BEOL互连和可扩展到ELK k≤2.3介电材料
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090370
K. Hamioud, V. Arnal, A. Farcy, V. Jousseaume, A. Zenasni, O. Gourhant, B. Icard, J. Pradelles, S. Manakli, P. Brun, G. Imbert, C. Jayet, M. Assous, S. Maitrejean, M. Vilmay, D. Galpin, C. Monget, J. Guillan, S. Chhun, E. Richard, D. Barbier, M. Haond
{"title":"Demonstration of TFHM scalability to 32 nm node BEOL interconnect and extendibility to ELK k ≤ 2.3 dielectric material","authors":"K. Hamioud, V. Arnal, A. Farcy, V. Jousseaume, A. Zenasni, O. Gourhant, B. Icard, J. Pradelles, S. Manakli, P. Brun, G. Imbert, C. Jayet, M. Assous, S. Maitrejean, M. Vilmay, D. Galpin, C. Monget, J. Guillan, S. Chhun, E. Richard, D. Barbier, M. Haond","doi":"10.1109/IITC.2009.5090370","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090370","url":null,"abstract":"A 32 nm node BEOL demonstrator using Trench First Hard Mask (TFHM) architecture is realized. The dual damascene process is performed with ELK dielectric at line and via level and with an adapted metallization in order to meet ITRS specifications. ELK k=2.3 & k=2.2 are studied in a TFHM architecture in order to prove its extendibility to ELK dielectric materials.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115658320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Double thick-polymer technology to realize low signal pad capacitance suitable for high-speed data transmission 采用双厚聚合物技术实现适合高速数据传输的低信号垫电容
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090348
K. Kikuchi, J. Sakai, K. Soejima, Shinya Funato, M. Kawano, H. Kouta, S. Yamamichi
{"title":"A Double thick-polymer technology to realize low signal pad capacitance suitable for high-speed data transmission","authors":"K. Kikuchi, J. Sakai, K. Soejima, Shinya Funato, M. Kawano, H. Kouta, S. Yamamichi","doi":"10.1109/IITC.2009.5090348","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090348","url":null,"abstract":"A Pad-on-Stacked-Polymer (PASPO) technology, based on low cost packaging process, has been developed by utilizing 13-µm-thick double polymer layers and modified signal land design. The bottom photosensitive polymer shows higher via-hole resolution and higher chemical tolerance than conventional passivation polymer. The highly-reliable top polymer is planarized by CMP. For the 20-µm-square signal land, the PASPO technology drastically reduces the signal pad capacitance from 173 fF to 11 fF, and a clear eye opening for 40 Gbps signal transmission has been achieved for the low-k test chip.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124835518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Defect study of manufacturing feasible porous low k dielectrics direct polish for 45nm technology and beyond 45纳米及以上多孔低钾电介质直接抛光工艺的缺陷研究
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090365
C. Hsu, J. Fang, A. Yu, J. Lin, C. Huang, J. Y. Wu, D. Perng
{"title":"Defect study of manufacturing feasible porous low k dielectrics direct polish for 45nm technology and beyond","authors":"C. Hsu, J. Fang, A. Yu, J. Lin, C. Huang, J. Y. Wu, D. Perng","doi":"10.1109/IITC.2009.5090365","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090365","url":null,"abstract":"In this paper, the specific 45nm direct polish related defects and its effects were investigated in order to achieve the high yield manufacturing feasibility of direct polish to porous low-k dielectric film. Crater defect (ring shape metal bridge) was identified caused by abrasive residue in the pre-metal layer polish. Polished with colloidal silica based Cu slurry could suppress this defect efficiently. The plasma treatment on porous ultra low-k (ULK) layer improved the adhesion. However, it induced peeling when polish stop at this treated interface. It could be removed if further polish to intact ULK film. High Cu roughness possibly induced both pattern missing and via open in the following metal layer and suffered the yields. The V1M2 upstream electro-migration (EM) at this generation highly correlated to the roughness degree. By optimizing clean chemical concentration and clean time satisfied the needs of Cu roughness. Yield improvement proved the manufacturing feasibility of ULK direct polish technology.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121422173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Advanced BEOL integration using porous low-k (k=2.25) material with charge damage-less electron beam cure technique 先进的BEOL集成采用多孔低k (k=2.25)材料与电荷无损伤电子束固化技术
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090368
T. Owada, N. Ohara, H. Watatani, T. Kouno, H. Kudo, H. Ochimizu, T. Sakoda, N. Asami, Y. Ohkura, S. Fukuyama, A. Tsukune, M. Nakaishi, T. Nakamura, Y. Nara, M. Kase
{"title":"Advanced BEOL integration using porous low-k (k=2.25) material with charge damage-less electron beam cure technique","authors":"T. Owada, N. Ohara, H. Watatani, T. Kouno, H. Kudo, H. Ochimizu, T. Sakoda, N. Asami, Y. Ohkura, S. Fukuyama, A. Tsukune, M. Nakaishi, T. Nakamura, Y. Nara, M. Kase","doi":"10.1109/IITC.2009.5090368","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090368","url":null,"abstract":"As a practical curing technique of low-k material for 32-nm BEOL technology node, we demonstrated that electron beam (e-beam) irradiation was effective to improve film properties of nano-clustering silica (NCS). We confirmed that by using optimized e-beam cure condition, NCS was successfully hardened without degradation of dielectric constant and the Young's modulus increased by 1.7 times compared with that of thermally cured NCS. We fabricated two-level Cu wirings layers with NCS cured by optimized e-beam cure technique. The e-beam cure dramatically enhanced the lifetime of time-dependent dielectric breakdown (TDDB) of interlayer dielectrics. We also examined the influence of the charge damage to the MOSFETs under e-beam cured NCS layer and confirmed that there was no e-beam charge damage to the Ion-Ioff characteristics and reliability of MOSFETs with the optimized e-beam cure.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123752160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low resistive and highly reliable copper interconnects in combination of silicide-cap with Ti-barrier for 32 nm-node and beyond 低电阻和高可靠的铜互连硅帽与ti屏障的32纳米节点及以上的组合
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090401
Y. Hayashi, N. Matsunaga, M. Wada, S. Nakao, K. Watanabe, A. Sakata, H. Shibata
{"title":"Low resistive and highly reliable copper interconnects in combination of silicide-cap with Ti-barrier for 32 nm-node and beyond","authors":"Y. Hayashi, N. Matsunaga, M. Wada, S. Nakao, K. Watanabe, A. Sakata, H. Shibata","doi":"10.1109/IITC.2009.5090401","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090401","url":null,"abstract":"Silicide-cap for Cu interconnects is promising for enhancing electromigration (EM) performance for 32 nm-node and beyond. But the trade-off properties of silicide-cap between line resistance and EM lifetime remain to be resolved. Increasing of line resistance is caused by Si diffusion in Cu line. So, we focused on Ti barrier metal (BM), which diffuses in Cu line, and applied it in combination with silicide-cap, in order to keep Si stable at the surface of Cu line. As a result, we achieved EM median time-to-failure (MTF) 100 times longer than that of the sample w/o silicide-cap and Ta-BM while line resistance is kept lower. Activation energy (Ea of EM of 1.45 eV is achieved.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127142466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Highly-reliable molecular-pore-stack (MPS)-SiOCH/Cu interconnects with CoWB metal-cap films 高可靠的分子孔堆栈(MPS)-SiOCH/Cu与cob金属帽膜互连
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090327
M. Tagami, N. Furutake, N. Inoue, E. Nakazawa, K. Arita, Y. Hayashi
{"title":"Highly-reliable molecular-pore-stack (MPS)-SiOCH/Cu interconnects with CoWB metal-cap films","authors":"M. Tagami, N. Furutake, N. Inoue, E. Nakazawa, K. Arita, Y. Hayashi","doi":"10.1109/IITC.2009.5090327","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090327","url":null,"abstract":"Highly-reliable molecular-pore-stack (MPS)-SiOCH (k=2.5)/Cu interconnects with CoWB metal-cap have been developed. The MPS-SiOCH film is suitable for CoWB metal-cap by self-aligned electroless plating because of its unique pore-structure such as small-closed pores in carbon-rich SiOCH matrix. The MPS-SiOCH film suppresses the Co diffusion into the film and metal residue on the surface during the metal-cap process, achieving high TDDB reliability as well as improving reliabilities of EM and SiV remarkably. A combination of the MPS-SiOCH/Cu line and the CoWB metal-cap is a strong candidate for highly reliable LSIs.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133456302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Enabling 3D interconnects with metal direct bonding 通过金属直接粘合实现3D互连
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090369
L. Di Cioccio, P. Gueguen, T. Signamarcheix, M. Rivoire, D. Scevolab, Regis Cahours, P. Leduc, M. Assous, L. Clavelier
{"title":"Enabling 3D interconnects with metal direct bonding","authors":"L. Di Cioccio, P. Gueguen, T. Signamarcheix, M. Rivoire, D. Scevolab, Regis Cahours, P. Leduc, M. Assous, L. Clavelier","doi":"10.1109/IITC.2009.5090369","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090369","url":null,"abstract":"This paper presents the implementation of a key technology developed for high density 3-D integration by circuit stacking. Direct copper bonding at room temperature, atmospheric pressure and ambient air of copper pads allowed the elaboration of a 10×10 9m vertical interconnect with a contact resistance of 10 mohms. First tests on tungsten bonding will be also reviewed.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"283 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122957782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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