用于45纳米以下技术节点的高可靠SiOCH低k电介质的关键工艺步骤

M. Vilmay, D. Roy, C. Besset, D. Galpin, C. Monget, P. Vannier, Y. Le Friec, G. Imbert, M. Mellier, S. Petitdidier, O. Robin, J. Guillan, S. Chhun, L. Arnaud, F. Volpi, J. Chaix
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引用次数: 4

摘要

在铜互连中引入SiOCH低k介电材料,与降低先进技术节点的关键尺寸相关,正在成为一个主要的可靠性问题。互连的实现需要相应的关键工艺步骤[1]。由于多孔低k介电体被用作金属间介电体(IMD),每个工艺步骤都可能是介电体退化的一个来源。本文介绍了影响低k可靠性的关键工艺步骤。所有影响介质接口的过程也被证明会降低低k互连的鲁棒性。本文详细介绍了直接化学和机械抛光(CMP)、浆料化学和TaN/Ta势垒刻蚀等工艺实例。此外,在不降低电性能的情况下,给出了一些工艺选择,以显著提高低k介电可靠性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Key Process steps for high reliable SiOCH low-k dielectrics for the sub 45nm technology nodes
The introduction of SiOCH low-k dielectrics in copper interconnects associated to the reduction of the critical dimensions in advanced technology nodes is becoming a major reliability concern. The interconnect realization requires a consequent number of critical process steps [1]. Since porous low-k dielectrics are used as Inter-Metal Dielectric (IMD) each process step can be a source of degradation for the dielectric. This paper describes critical process steps influencing the low-k reliability. All the processes affecting the dielectric's interfaces are also evidenced to degrade the low-k interconnect robustness. Some process examples as the direct chemical and mechanical polishing (CMP), the slurry chemistry and the TaN/Ta barrier etching are details in this paper. Moreover, some process options are given to strongly improve low-k dielectric reliability without degradation of its electrical performances.
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