优化集成铜隙填充方法的2x闪存器件

P. Ma, Qian Luo, A. Sundarrajan, J. Lu, J. Aubuchon, J. Tseng, Niranjan Kumar, M. Okazaki, Yuchun Wang, You Wang, Yufei Chen, M. Naik, I. Emesh, M. Narasimhan
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引用次数: 9

摘要

物理气相沉积(PVD) Cu种子层已经成功地用于22nm闪存器件的特征尺寸Cu间隙填充。通过调整Cu离子入射通量的入射角以及利用溅射参数,可以很好地控制悬垂、侧壁覆盖和不对称性,从而实现后续电化学沉积(ECD)的完全填充。还研究了化学气相沉积(CVD)钴(Co)膜作为Cu隙填充的增强层。在PVD Ta阻挡层和Cu种子层之间插入1.5nm厚的CVD Co层,可以有效地增强小几何沟槽/通孔结构中的间隙填充。CVD Co增强层还可以显著提高Cu互连的电迁移(EM)电阻。化学机械抛光(CMP)工艺也被开发出来,以提供一个集成的解决方案。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimized integrated copper gap-fill approaches for 2x flash devices
Physical vapor deposited (PVD) Cu seed layers have been successfully implemented for Cu gap-fill in feature sizes for the 2x nm flash devices. By tuning the incident angle of the incoming flux of Cu ions as well as utilizing the resputtering parameter, the overhang, sidewall coverage and asymmetry can be well controlled to enable complete fill by subsequent electrochemical deposition (ECD). Chemical vapor deposition (CVD) Cobalt (Co) films were also investigated as an enhancement layer for Cu gap-fill. It was observed that the insertion of a 1.5nm-thick CVD Co layer, deposited between a PVD Ta barrier and a Cu seed layer could effectively enhance gap-fill in the small geometry trench/via structures. The CVD Co enhancement layer could also significantly improve the electromigration (EM) resistance of the Cu interconnects. The Chemical Mechanical Polish (CMP) process was also developed to provide an integrated solution.
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