{"title":"芯片封装相互作用对大芯片倒装封装中Cu/超低k互连分层的影响","authors":"C. Uchibori, Michael Lee","doi":"10.1109/IITC.2009.5090392","DOIUrl":null,"url":null,"abstract":"Die size effects on Chip Package Interaction for Cu/Ultra low-k interconnect in Flip Chip Package were investigated using mechanical and thermal analysis. The analytical and the theoretical study suggested that the die size effects were not caused only by the mismatch in CTE between die and substrate. By considering the number of bonding solder and its mechanical property during the cooling process, the die size dependency of CPI was successfully demonstrated.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"45 10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Impact of chip package interaction on Cu/Ultra low-k interconnect delamination in Flip Chip Package with large die\",\"authors\":\"C. Uchibori, Michael Lee\",\"doi\":\"10.1109/IITC.2009.5090392\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Die size effects on Chip Package Interaction for Cu/Ultra low-k interconnect in Flip Chip Package were investigated using mechanical and thermal analysis. The analytical and the theoretical study suggested that the die size effects were not caused only by the mismatch in CTE between die and substrate. By considering the number of bonding solder and its mechanical property during the cooling process, the die size dependency of CPI was successfully demonstrated.\",\"PeriodicalId\":301012,\"journal\":{\"name\":\"2009 IEEE International Interconnect Technology Conference\",\"volume\":\"45 10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE International Interconnect Technology Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2009.5090392\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Interconnect Technology Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2009.5090392","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of chip package interaction on Cu/Ultra low-k interconnect delamination in Flip Chip Package with large die
Die size effects on Chip Package Interaction for Cu/Ultra low-k interconnect in Flip Chip Package were investigated using mechanical and thermal analysis. The analytical and the theoretical study suggested that the die size effects were not caused only by the mismatch in CTE between die and substrate. By considering the number of bonding solder and its mechanical property during the cooling process, the die size dependency of CPI was successfully demonstrated.