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Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)最新文献

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Temperature distributions in III-V microwave power transistors using spatially resolved photoluminescence mapping 利用空间分辨光致发光作图的III-V型微波功率晶体管温度分布
Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869853
J. Landesman, D. Floriot, E. Martín, R. Bisaro, S. Delage, P. Braun
{"title":"Temperature distributions in III-V microwave power transistors using spatially resolved photoluminescence mapping","authors":"J. Landesman, D. Floriot, E. Martín, R. Bisaro, S. Delage, P. Braun","doi":"10.1109/ICCDCS.2000.869853","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869853","url":null,"abstract":"This paper describes a new method for the mapping of local temperatures in the active region of high power III-V semiconductor transistors for microwave applications. The measurement technique involves scanning a focused laser beam at the surface of a chip inside its package, while the photoluminescence (PL) spectra produced are recorded sequentially for each position of the laser beam. The local temperature is deduced from the corresponding wavelength shift of the PL peak, which represents changes in the band-gap due to heating. Results are shown both for field effect type transistors (pseudomorphic high electron mobility transistors-PHEMTs-in the GaAs/Ga/sub 1-x/Al/sub x/As/Ga/sub 1-y/In/sub y/As system) and for bipolar type transistors (heterojunction bipolar transistors-HBTs-in the GaAs/Ga/sub 1-x/In/sub x/P system). A spatial resolution of 1 /spl mu/m and an accuracy in the temperature determination of /spl plusmn/1/spl deg/C are demonstrated, especially for the PHEMTs. Finally, procedures are proposed to implement the information on local operating temperatures provided by this method into thermal resistance calculations.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122869640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of low emission integrated circuits 低发射集成电路的设计
Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869805
E. Sicard, S. Delmas Bendhia
{"title":"Design of low emission integrated circuits","authors":"E. Sicard, S. Delmas Bendhia","doi":"10.1109/ICCDCS.2000.869805","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869805","url":null,"abstract":"This paper describes a set of efficient design techniques, which reduce significantly the parasitic emission of CMOS integrated circuits. Both layout level and package-related guidelines are presented. Most of these techniques are being applied successfully in state of the art 0.25 /spl mu/m CMOS designs.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128512170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Radiation-stable solid state devices based on intrinsic semiconductors 基于本征半导体的辐射稳定固态器件
Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869827
Y. Gurevich, I. Volovichev, V. Koshkin
{"title":"Radiation-stable solid state devices based on intrinsic semiconductors","authors":"Y. Gurevich, I. Volovichev, V. Koshkin","doi":"10.1109/ICCDCS.2000.869827","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869827","url":null,"abstract":"The perspective of use of radiation-stable semiconductor compounds with loose crystal structures for development of solid state devices is discussed. The theoretical possibility of creation of active electronic elements based on semiconductors of this type is shown. A feasible implementation of the solid-state amplifier on the basis of thin-film heterostructures of intrinsic semiconductors is suggested and its parameters are calculated.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130585215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Spin on glass as an antireflection layer on amorphous absorption layer photodetectors 自旋在玻璃上作为非晶吸收层光电探测器的抗反射层
Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869850
A. Jacome, A. M. Castillo, C. Z. Islas
{"title":"Spin on glass as an antireflection layer on amorphous absorption layer photodetectors","authors":"A. Jacome, A. M. Castillo, C. Z. Islas","doi":"10.1109/ICCDCS.2000.869850","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869850","url":null,"abstract":"A silicon based Separated-Absorption-Multiplication Avalanche Photo Diode (SAMAPD) is coated with Spin On Glass (SOG) as an antireflection (AR) layer. The curing temperature is only 200/spl deg/C, for curing times ranging from 6 to 10 hours. It is demonstrated that the refractive index and thickness of the SOG can be controlled. The SAMAPD with an AR layer shows an improvement in the photocurrent up to 20% at 0.85 /spl mu/m when compared with that without AR layer. A flat response in the range 0.8-0.9 /spl mu/m is observed when the photocurrent of the AR coated SAMAPD is measured.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130963758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Laser interconnects based multi-FPGA system 基于激光互连的多fpga系统
Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869847
V. Pasham, F.J. Falquez, W. A. Moreno
{"title":"Laser interconnects based multi-FPGA system","authors":"V. Pasham, F.J. Falquez, W. A. Moreno","doi":"10.1109/ICCDCS.2000.869847","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869847","url":null,"abstract":"The major concern of ASIC designers is the long design cycle time. Researchers have been performing extensive research using multi-FPGA systems for ASIC implementation. The key aspects of designing such a system are precise architecture, type of programming interconnect, routing topology etc. This paper proposes an innovative multi-FPGA system using laser based programmable interconnects and antifuse FPGAs, integrated on an MCM. This multi-FPGA system has better performance then conventional PCB board based multi-FPGA systems due to inherent advantages of the MCM over board systems coupled with faster programmable interconnects.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127655243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An integrated DC-to-AC converter for electroluminescent displays 用于电致发光显示器的集成dc - ac转换器
Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869860
W. Doll, T. Junker, R. Minder
{"title":"An integrated DC-to-AC converter for electroluminescent displays","authors":"W. Doll, T. Junker, R. Minder","doi":"10.1109/ICCDCS.2000.869860","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869860","url":null,"abstract":"This paper presents an integrated mixed-signal DC-to-AC converter for electroluminescent (EL) displays, featuring a digital synthesis of the required output waveform. The circuit is integrated with a 2.0 /spl mu/m 50 V CMOS technology and is capable of driving EL displays with a power consumption of up to 4.5 VA. It is suitable for standalone applications as well as for applications in clusters digitally controlled by a microcomputer.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124383533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low noise, high linearity and low power BiCMOS mixer for RF applications 低噪声，高线性和低功耗的BiCMOS混频器用于射频应用
Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869800
S. Colomines, T. Arnaud, T. Parra, J. Graffeuil, R. Plana
{"title":"Low noise, high linearity and low power BiCMOS mixer for RF applications","authors":"S. Colomines, T. Arnaud, T. Parra, J. Graffeuil, R. Plana","doi":"10.1109/ICCDCS.2000.869800","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869800","url":null,"abstract":"This paper presents a low IF mixer featuring MOS devices in the RF and the active load stages for DCS applications which have been optimized with respect to the supply voltage (2.2 V), current consumption (<10 mA), gain (10 dB), linearity (IIP3=8.5 dBm) and noise (DSB Nf=13 dB @100 kHz).","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116369795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The threshold voltage model of a SOI-MOSFET on films with Gaussian profile 高斯分布薄膜上SOI-MOSFET的阈值电压模型
Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869846
Cristian Ravariu, Adrian Rusu, F. Ravariu, Dobrescu, '. LidiaDobrescu, Politechnica
{"title":"The threshold voltage model of a SOI-MOSFET on films with Gaussian profile","authors":"Cristian Ravariu, Adrian Rusu, F. Ravariu, Dobrescu, '. LidiaDobrescu, Politechnica","doi":"10.1109/ICCDCS.2000.869846","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869846","url":null,"abstract":"The analytical models for electric field and potential distributions are useful for a lot of SOI devices, like SOI-MOSFET, SOI-BJT, three-dimensional device, SOI sensors and the others. For example, they are necessary for establish the inversion or accumulation conditions for front and back interfaces. The paper refers to a one-dimensional analysis, both for partially and fully depleted devices on films with nonuniform doping. The goal of this paper is to obtain an accurate model for the field and the potential distribution in the SOI structures with Gaussian doping concentration of impurities in the film. The results have been used for threshold voltage deduction, but they represent a reference point in developing of new models for SOI-devices fabricated on Gaussian profile films. In the fully depleted films case, the depletion of the silicon substrate for gate voltages that entirely depleted the film was considered. The results were compared with PISCES numerical simulations and were in good agreement.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132301919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fundamental scaling laws of DRAM dielectrics DRAM介电体的基本标度定律
Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869832
H. Reisinger, R. Stengl
{"title":"Fundamental scaling laws of DRAM dielectrics","authors":"H. Reisinger, R. Stengl","doi":"10.1109/ICCDCS.2000.869832","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869832","url":null,"abstract":"Dynamic random access memories (DRAM) demand an ever increasing density of storage capacitors. We show that increasing the dielectric constant K of the capacitor dielectric will not help to meet future requirements. This is because the amount of charge stored on a given area has an upper physical limit. In fact if the scaling of DRAM feature sizes and supply voltages will follow the SIA roadmap, a maximum K-value of 500 to 1000 must not be exceeded for future DRAM generations.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125361230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Impact of inductance on timing characteristics of VLSI interconnects 电感对VLSI互连时序特性的影响
Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869801
G. Servel, F. Huret, E. Paleczny, P. Kennis, D. Deschacht
{"title":"Impact of inductance on timing characteristics of VLSI interconnects","authors":"G. Servel, F. Huret, E. Paleczny, P. Kennis, D. Deschacht","doi":"10.1109/ICCDCS.2000.869801","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869801","url":null,"abstract":"As the result of the scaling down of technology and increased chip sizes, the cross-sectional area of wires has been reduced. With these trends, it is becoming crucial to be able to determine which nets within a high speed VLSI circuit exhibit prominent inductive effects. The object of this paper is to answer a question frequently put to designers: is inductance necessary to model interconnections or can a simple RC model be sufficient? By comparing the simulation results obtained from electrical simulations to an electromagnetic approach we can verify if the RC distributed model is always sufficient to characterize the propagation delay and the degradation due to the interconnect lines in submicronic circuit. Limits between RC and RLC models are determined.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123002224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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