Design of low emission integrated circuits

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI:10.1109/ICCDCS.2000.869805

E. Sicard, S. Delmas Bendhia

引用次数: 0

Abstract

This paper describes a set of efficient design techniques, which reduce significantly the parasitic emission of CMOS integrated circuits. Both layout level and package-related guidelines are presented. Most of these techniques are being applied successfully in state of the art 0.25 /spl mu/m CMOS designs.

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低发射集成电路的设计

本文介绍了一套有效的设计技术，可以显著降低CMOS集成电路的寄生发射。给出了布局级别和包相关的指导方针。这些技术中的大多数都成功地应用于最先进的0.25 /spl μ m CMOS设计中。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)

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