{"title":"Verilog-A and Verilog-AMS provides a new dimension in modeling and simulation","authors":"I. Miller, T. Cassagnes","doi":"10.1109/ICCDCS.2000.869811","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869811","url":null,"abstract":"Verilog-A provides a new dimension in modeling, design and simulation capability for analog and mixed signal electronic systems. Previously, analog simulation has been based upon Spice, which is a very effective simulation environment based on primitives such as transistors, resistors, and capacitors. Digital design verification is based on a Hardware Description Language (HDL). Verilog and Verilog derivatives have been widely accepted due to their ease of use and gate level simulation capability. Verilog, which accounted for more than 60% of the HDL simulator sales in 1997, has a strong following with a host of tools that complement the language and extend the capability to verification and test. This paper presents the motivation for the Verilog-A language, an extension of Verilog to describe analog and non-electrical behavior, and illustrates the Verilog-A language via short examples and a overview of an ink jet printer ASIC support IC behavioral model.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114539400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Belverde, A. Galluzzo, M. Melito, S. Musumeci, A. Raciti
{"title":"On the series connection of insulated gate power devices","authors":"G. Belverde, A. Galluzzo, M. Melito, S. Musumeci, A. Raciti","doi":"10.1109/ICCDCS.2000.869865","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869865","url":null,"abstract":"The series connection of insulated gate devices (IGBTs and MOSFETs) is treated with reference to different approaches which ensure a balanced voltage sharing. Both load-side and gate-side techniques are discussed, and their merits and demerits are highlighted. A novel approach, which intervenes during the rise time or fall time of the collector voltages, is discussed and compared to the alternative solutions. Laboratory tests on two IGBT devices are carried out according to the analyzed techniques. Finally, the disadvantages of the multiple connections are discussed in terms of switching speed reduction and power loss increase.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133836126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A nonlinear theory of near-carrier phase noise in free-running oscillators","authors":"G. Klimovitch","doi":"10.1109/ICCDCS.2000.869882","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869882","url":null,"abstract":"A general nonlinear theory of near-carrier phase noise in oscillators is presented. It is developed in terms of the linear dependence of the instantaneous frequency of oscillations on small-signal noise. The theory is applied to a Colpitts FET oscillator in the short-channel regime. Phase noise due to amplitude to phase conversion is given special attention, since it can dominate in high-Q tunable oscillators. The theory agrees with existing linear phase noise models at frequencies where these models are valid, but predicts new phenomena at frequencies very close to the carrier. In this frequency range, the dependence of noise-induced shift in oscillator phase on noise becomes nonlinear even for small-signal noise, while the instantaneous frequency remains a linear function of noise. As a result, the oscillator line shape qualitatively differs from predictions of linear models. In particular, 1/f circuit noise results in an approximately Gaussian line shape of a free-running oscillator in the immediate vicinity of the carrier. In a significant part of this frequency region, the noise spectral density is proven to be much larger than the conventional models predict. The proposed theory gives new insights Into low noise design and is suitable for both computer and hand estimates of near-carrier phase noise.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128868002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparison of adaptive equalization methods for the ATSC and DVB-T digital television broadcast systems","authors":"F. Eory","doi":"10.1109/ICCDCS.2000.869890","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869890","url":null,"abstract":"The ATSC and DVB-T international standards for terrestrial digital television broadcasting employ substantially different data transmission schemes and employ fundamentally different techniques for adaptive equalization of time-varying frequency-selective fading channels. These differences, as well as the different percentages of the channel capacity dedicated to training signals, have significant effects on the degree of time variation that can be tracked by these equalizers, as well as on the carrier to noise ratio penalty associated with equalization. Performance comparisons of a recently developed ATSC adaptive equalizer with previously published DVB-T results demonstrate that for stationary reception of digital television signals, the new ATSC equalizer is capable of canceling strong multipath echoes at the dynamic phase rotation rates typical of stationary reception, while maintaining the C/N advantage that ATSC has over DVB-T in Gaussian channels. DVB-T equalizers continue to hold an advantage in tracking high frequency dynamics associated with mobile reception, but with a C/N penalty that increases with echo phase rotation rate.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121544470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low power 900 MHz PLL frequency synthesizer for ISM applications using 0.25 /spl mu/m BiCMOS","authors":"K. Huehne, D. Lovelace, P. Ovalle","doi":"10.1109/ICCDCS.2000.869806","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869806","url":null,"abstract":"MOS Current Mode Logic (CML) is featured on a 0.25 /spl mu/m BiCMOS technology to implement a low noise, low power PLL operating to 1.2 GHz for portable wireless applications. It operates over 1.8 to 2.8 V and consumes 9.3 mA including the VCO. As part of a highly integrated two-chip transceiver system, full differential operation significantly reduces phase noise.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132200641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An equivalent circuit model for IGBT","authors":"C. Kao, Yat-Chin Liang","doi":"10.1109/ICCDCS.2000.869852","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869852","url":null,"abstract":"A new circuit model for the IGBT is developed. This model uses the transmission-line circuit technique and is suitable for circuit simulators. The new circuit model for the IGBT is implemented into widely used SPICE3 and all the simulation results are compared with the results of the TMA MEDICI device simulator.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133978863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Process considerations in reducing leakage current of PIN radiation detectors","authors":"D. Resnik, D. Križaj, D. Vrtacnik, S. Amon","doi":"10.1109/ICCDCS.2000.869830","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869830","url":null,"abstract":"PIN diode structures for radiation detection were designed and fabricated on high resistivity silicon wafers by means of planar process. Technological process development of the device and resulting electrical characteristics are presented. Extrinsic gettering with polysilicon and n/sup +/ phosphorus doped back side layer was employed. Surface passivation with dry or wet thermal oxide in combination with silicon nitride was performed in order to reduce surface leakage current over top p/sup +/ boron doped active area. Moreover, thermal budget was kept as low as possible due to preservation of bulk lifetime. Total leakage current as one of the most adequate parameter to evaluate process was monitored on fabricated radiation detectors and test structures. Best average values of leakage current density achieved were in low nA/cm/sup 2/ range per 100 /spl mu/m depletion width for the case of gettering with LPCVD polysilicon phosphorus doped layer on the rear side.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115423715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A quadrature down converter for direct conversion receivers with high 2nd and 3rd order intercept points","authors":"B. Bastani, E. Bautista, G. Nagaraj, J. Heck","doi":"10.1109/ICCDCS.2000.869802","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869802","url":null,"abstract":"This paper describes an I and Q down converter designed for a 800 MHz direct conversion receiver. The down converter employs a bipolar Gilbert cell mixer with degenerated common base input stage that achieves greater than +62 dBm 2nd order input intercept point (IIP2) and +6 dBm 3rd order input intercept point (IIP3) with 4.6 mA at 2.5 Volt. The use of a fully balanced, fully differential topology and divide-by-two quadrature generator has improved the LO to RF signal isolation to better than 85 dB.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115471979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Aller, A. Bueno, T. Paga, J. Restrepo, V. Guzmán, M. Giménez
{"title":"Space vector applications in power systems","authors":"J. Aller, A. Bueno, T. Paga, J. Restrepo, V. Guzmán, M. Giménez","doi":"10.1109/ICCDCS.2000.869863","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869863","url":null,"abstract":"The spatial vector transformation, as used in machine vector control, is applied to power system analysis. The proposed methodology is applied to power electronics converters, transformers and transmission lines, as well as to power sources and loads with different connections (delta-wye). This method can be applied to steady-state, transient, unbalanced sources and harmonic analysis. Models obtained using this method are as simple as the per-phase schematic approach. The instantaneous active and reactive power concepts can be expanded and generalized, and new power system control strategies can be developed when power electronics converters are used. Steady-state, transient behavior and harmonic analysis examples and applications using spatial vector theory are presented in order to illustrate the methodology's performance and its advantages. An extension of this method can be applied to faulted systems (unbalanced) using instantaneous symmetric components in poly-phase balanced circuits.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116795056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A dynamic threshold-voltage SOI MOSFET with a stepped channel doping profile","authors":"Jun Xu, M. Cheng","doi":"10.1109/ICCDCS.2000.869834","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869834","url":null,"abstract":"A novel dynamic threshold voltage SOI MOS structure with a stepped-channel-doping (SCD) profile is proposed. The influence of the SCD profile on performance of deep-submicron dynamic threshold SOI MOSFET's is studied systematically using two-dimensional device simulation. It is discovered that the SCD configuration combined with the dynamic threshold SOI MOS structure not only effectively suppresses short-channel effects, but also greatly enhances the device driving capability. Moreover, the heavily doped body in the SCD device substantially reduces the forward-biased body current and source-drain punch-through current.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127263282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}