一款低功耗900 MHz锁相环频率合成器，适用于使用0.25 /spl mu/m BiCMOS的ISM应用

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-17 DOI:10.1109/ICCDCS.2000.869806

K. Huehne, D. Lovelace, P. Ovalle

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引用次数: 1

摘要

MOS电流模式逻辑(CML)采用0.25 /spl mu/m BiCMOS技术，实现低噪声，低功耗锁相环，工作频率为1.2 GHz，适用于便携式无线应用。它的工作电压为1.8至2.8 V，包括压控振荡器在内的功耗为9.3 mA。作为高度集成的双芯片收发器系统的一部分，全差分操作显著降低了相位噪声。

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A low power 900 MHz PLL frequency synthesizer for ISM applications using 0.25 /spl mu/m BiCMOS

MOS Current Mode Logic (CML) is featured on a 0.25 /spl mu/m BiCMOS technology to implement a low noise, low power PLL operating to 1.2 GHz for portable wireless applications. It operates over 1.8 to 2.8 V and consumes 9.3 mA including the VCO. As part of a highly integrated two-chip transceiver system, full differential operation significantly reduces phase noise.

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Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)

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